IDT82V3380PF8 IDT, Integrated Device Technology Inc, IDT82V3380PF8 Datasheet - Page 5

• Manufacturer Part Number: IDT82V3380PF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3380PF8

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Table of Contents
9 ELECTRICAL SPECIFICATIONS .................................................................................................................................. 152
IDT82V3380
8.2 EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................................................... 151
8.3 HEATSINK EVALUATION .......................................................................................................................................................................... 151
9.1 ABSOLUTE MAXIMUM RATING ................................................................................................................................................................ 152
9.2 RECOMMENDED OPERATION CONDITIONS .......................................................................................................................................... 152
9.3 I/O SPECIFICATIONS ................................................................................................................................................................................. 153
9.4 JITTER & WANDER PERFORMANCE ....................................................................................................................................................... 159
9.5 OUTPUT WANDER GENERATION ............................................................................................................................................................ 162
9.6 INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................. 163
9.7 OUTPUT CLOCK TIMING ........................................................................................................................................................................... 164
ORDERING INFORMATION .......................................................................................................................................... 170
9.3.1
9.3.2
9.3.3
AMI Input / Output Port ................................................................................................................................................................ 153
9.3.1.1
9.3.1.2
9.3.1.3
CMOS Input / Output Port ............................................................................................................................................................ 155
PECL / LVDS Input / Output Port ................................................................................................................................................ 156
9.3.3.1
9.3.3.2
Structure ......................................................................................................................................................................... 153
I/O Level ......................................................................................................................................................................... 153
Over-Voltage Protection ................................................................................................................................................. 155
PECL Input / Output Port ................................................................................................................................................ 156
LVDS Input / Output Port ................................................................................................................................................ 158
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SYNCHRONOUS ETHERNET WAN PLL
October 20, 2008