IDT82V3380PF8 IDT, Integrated Device Technology Inc, IDT82V3380PF8 Datasheet - Page 7

• Manufacturer Part Number: IDT82V3380PF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3380PF8

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

IDT82V3380
SYNCHRONOUS ETHERNET WAN PLL
Table 49: AMI Input / Output Port Electrical Characteristics ...................................................................................................................................... 154
Table 50: CMOS Input Port Electrical Characteristics ............................................................................................................................................... 155
Table 51: CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics ................................................................................................ 155
Table 52: CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics ........................................................................................... 155
Table 53: CMOS Output Port Electrical Characteristics ............................................................................................................................................ 155
Table 54: PECL Input / Output Port Electrical Characteristics ................................................................................................................................... 157
Table 55: LVDS Input / Output Port Electrical Characteristics ................................................................................................................................... 158
Table 56: Output Clock Jitter Generation .................................................................................................................................................................. 159
Table 57: Output Clock Phase Noise ......................................................................................................................................................................... 160
Table 58: Input Jitter Tolerance (155.52 MHz) .......................................................................................................................................................... 160
Table 59: Input Jitter Tolerance (1.544 MHz) ............................................................................................................................................................ 160
Table 60: Input Jitter Tolerance (2.048 MHz) ............................................................................................................................................................ 160
Table 61: Input Jitter Tolerance (8 kHz) .................................................................................................................................................................... 160
Table 62: T0 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... 161
Table 63: T4 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... 161
Table 64: Input/Output Clock Timing 3 ...................................................................................................................................................................... 163
Table 65: Output Clock Timing .................................................................................................................................................................................. 165
List of Tables
7
October 20, 2008