IDT82V3380PF8 IDT, Integrated Device Technology Inc, IDT82V3380PF8 Datasheet - Page 8

• Manufacturer Part Number: IDT82V3380PF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3380PF8

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

List of Figures
Figure 1. Functional Block Diagram ............................................................................................................................................................................ 11
Figure 2. Pin Assignment (Top View) .......................................................................................................................................................................... 12
Figure 3. Pre-Divider for An Input Clock ..................................................................................................................................................................... 21
Figure 4. Input Clock Activity Monitoring ..................................................................................................................................................................... 23
Figure 5. External Fast Selection ................................................................................................................................................................................ 25
Figure 6. Qualified Input Clocks for Automatic Selection ............................................................................................................................................ 26
Figure 7. T0 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 32
Figure 8. T4 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 33
Figure 9. On Target Frame Sync Input Signal Timing ................................................................................................................................................. 44
Figure 10. 0.5 UI Early Frame Sync Input Signal Timing ............................................................................................................................................. 44
Figure 11. 0.5 UI Late Frame Sync Input Signal Timing .............................................................................................................................................. 45
Figure 12. 1 UI Late Frame Sync Input Signal Timing ................................................................................................................................................. 45
Figure 13. Physical Connection Between Two Devices .............................................................................................................................................. 46
Figure 14. IDT82V3380 Power Decoupling Scheme ................................................................................................................................................... 48
Figure 15. Typical Application ...................................................................................................................................................................................... 49
Figure 16. EPROM Access Timing Diagram ............................................................................................................................................................... 51
Figure 17. Multiplexed Read Timing Diagram ............................................................................................................................................................. 52
Figure 18. Multiplexed Write Timing Diagram .............................................................................................................................................................. 53
Figure 19. Intel Read Timing Diagram ......................................................................................................................................................................... 54
Figure 20. Intel Write Timing Diagram ......................................................................................................................................................................... 55
Figure 21. Motorola Read Timing Diagram .................................................................................................................................................................. 56
Figure 22. Motorola Write Timing Diagram .................................................................................................................................................................. 57
Figure 23. Serial Read Timing Diagram (CLKE Asserted Low) ................................................................................................................................... 58
Figure 24. Serial Read Timing Diagram (CLKE Asserted High) .................................................................................................................................. 58
Figure 25. Serial Write Timing Diagram ....................................................................................................................................................................... 59
Figure 26. JTAG Interface Timing Diagram ................................................................................................................................................................. 60
Figure 27. 64 kHz + 8 kHz Signal Structure .............................................................................................................................................................. 153
Figure 28. 64 kHz + 8 kHz + 0.4 kHz Signal Structure .............................................................................................................................................. 153
Figure 29. 64 kHz + 8 kHz / 64 kHz + 8 kHz + 0.4 kHz Signal Input Level ................................................................................................................ 153
Figure 30. 64 kHz + 8 kHz / 64 kHz + 8 kHz + 0.4 kHz Signal Output Level ............................................................................................................. 153
Figure 31. AMI Input / Output Port Line Termination (Recommended) ..................................................................................................................... 154
Figure 32. Recommended PECL Input Port Line Termination .................................................................................................................................. 156
Figure 33. Recommended PECL Output Port Line Termination ................................................................................................................................ 156
Figure 34. Recommended LVDS Input Port Line Termination .................................................................................................................................. 158
Figure 35. Recommended LVDS Output Port Line Termination ................................................................................................................................ 158
Figure 36. Output Wander Generation ...................................................................................................................................................................... 162
Figure 37. Input / Output Clock Timing ...................................................................................................................................................................... 163
List of Figures
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October 20, 2008