WG82574L S LBA8 Intel, WG82574L S LBA8 Datasheet - Page 266

• Manufacturer Part Number: WG82574L S LBA8
• Manufacturer: Intel

Specifications of WG82574L S LBA8

• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

9.1.6.2
9.1.6.2.1
266
PCIe Extended Configuration Space
PCIe configuration space is located in a flat memory-mapped address space. PCIe
extends the configuration space beyond the 256 bytes available for PCI to 4096 bytes.
The 82574 decodes additional 4-bits (bits 27:24) to provide the additional configuration
space as shown. PCIe reserves the remaining 4 bits (bits 31:28) for future expansion of
the configuration space beyond 4096 bytes.
The configuration address for a PCIe device is computed using PCI-compatible bus,
device and function numbers as follows:
PCIe extended configuration space is allocated using a linked list of optional or required
PCIe extended capabilities following a format resembling PCI capability structures. The
first PCIe extended capability is located at offset 0x100 in the device configuration
space. The first Dword of the capability structure identifies the capability/version and
points to the next capability.
The 82574 supports the following PCIe extended capabilities:
Advanced Error Reporting Capability
The PCIe advanced error reporting capability is an optional extended capability to
support advanced error reporting. The following table lists the PCIe advanced error
reporting extended capability structure for PCIe devices.
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C:0x28
0000b
• Advanced error reporting capability - offset 0x100
• Device serial number capability - offset 0x140
31
Register
Offset
28
PCIe CAP ID
Uncorrectable Error
Status
Uncorrectable Error
Mask
Uncorrectable Error
Severity
Correctable Error
Status
Correctable Error
Mask
First Error Pointer
Header Log
Bus #
27
Field
20
PCIe Extended Capability ID.
Reports error status of individual uncorrectable error sources on a PCIe
device.
Controls reporting of individual uncorrectable errors by device to the
host bridge via a PCIe error message.
Controls whether an individual uncorrectable error is reported as a fatal
error.
Reports error status of individual correctable error sources on a PCIe
device.
Controls reporting of individual correctable errors by device to the host
bridge via a PCIe error message.
Identifies the bit position of the first uncorrectable error reported in the
Uncorrectable Error Status register.
Captures the header for the transaction that generated an error.
Device #
19
15
82574 GbE Controller—Programing Interface
Fun #
14
Description
12
Register Address (offset)
11
2
00b
1 0