WG82574L S LBA8 Intel, WG82574L S LBA8 Datasheet - Page 323

• Manufacturer Part Number: WG82574L S LBA8
• Manufacturer: Intel

Specifications of WG82574L S LBA8

• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

Driver Programing Interface—82574 GbE Controller
10.2.5.8
Note:
10.2.5.9
Note:
10.2.5.10
Receive Descriptor Head - RDH (0x02810 + n*0x100[n=0..1]; RW)
This register contains the head pointer for the receive descriptor buffer. The register
points to a 16-byte datum. Hardware controls the pointer. The only time that software
should write to this register is after a reset (hardware reset or CTRL.RST) and before
enabling the receive function (RCTL.EN). If software were to write to this register while
the receive function was enabled, the on-chip descriptor buffers might be invalidated
and the hardware could be become unstable.
This register's address has been moved from where it was located in previous devices.
However, for backwards compatibility, this register can also be accessed at its alias
offset of 0x00120.
Receive Descriptor Tail - RDT (0x02818 + n*0x100[n=0..1]; RW)
This register contains the tail pointers for the receive descriptor buffer. The register
points to a 16-byte datum. Software writes the tail register to add receive descriptors
to the hardware free list for the ring.
This register's address has been moved from where it was located in previous devices.
However, for backwards compatibility, this register can also be accessed at its alias
offset of 0x00128.
Rx Interrupt Delay Timer [Packet Timer] - RDTR (0x02820; RW)
This register is used to delay interrupt notification for the receive descriptor ring by
coalescing interrupts for multiple received packets. Delaying interrupt notification helps
maximize the number of receive packets serviced by a single interrupt.
RDH
Reserved
RDT
Reserved
Delay
Reserved
FPD
Field
Field
Field
15:0
31:16
15:0
31:16
15:0
30:16
31
Bit(s)
Bit(s)
Bit(s)
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Initial
Initial
Initial
Value
Value
Value
Receive Descriptor Head
Reserved
Should be written with 0x0
Receive Descriptor Tail
Reads as 0x0. Should be written to 0x0 for future compatibility.
Receive packet delay timer measured in increments of 1.024 s.
Reserved
Reads as 0x0
Flush Partial Descriptor Block
When set to 1b, flushes the partial descriptor block; ignored
otherwise. Reads 0b.
Description
Description
Description
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