WG82574L S LBA8 Intel, WG82574L S LBA8 Datasheet - Page 58

• Manufacturer Part Number: WG82574L S LBA8
• Manufacturer: Intel

Specifications of WG82574L S LBA8

• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

3.3.8.6
3.4
Note:
3.5
Note:
Note:
58
Flash Programming Flow of S0 and S1
Other than initial programming of the Flash device, software and firmware should not
access the configuration sectors: S0 and S1. Any access to the configuration flow
should go to the Shadow RAM via the EEPROM interface registers.
System Management Bus (SMBus)
The NC-SI and SMBus interfaces cannot be used together in the same implementation.
One or the other is selected by the NVM image and loaded into the Flash.
SMBus is a low speed (100 KHz) serial bus used to connect various components in a
system for manageability purposes. SMBus is used as an interface to pass traffic
between the Manageability Controller (MC) and the 82574. The interface can also be
used to enable the MC to configure the 82574’s filters and management related
capabilities. Any device on the bus can be a master or a slave.
The SMBus uses two primary signals: SMBCLK and SMBDAT, to communicate. the
82574's SMB_CLK and SMB_DATA pins correspond to these signals. Both of these
signals float high with board-level pull-ups.
The SMBus specification has defined various types of message protocols composed of
individual bytes. The message protocols supported by the 82574 are described in
section
For more details about SMBus, see the SMBus specification and
NC-SI
The NC-SI interface in the 82574 is a connection to an external MC. It operates as a
single interface with an external MC, where all traffic between the 82574 and the MC
flows through the interface. See
The NC-SI and SMBus interfaces cannot be used together in the same implementation.
One or the other is selected by the NVM image and loaded into the Flash.
It is recommended that
prevent the pause effect from a flow control packet that might arrive from the LAN.
10. After all bytes are written to the Flash, hardware completes the cycle on the SPI
8. Until new data is written to the FLSWDATA register, the Flash clock is paused.
9. Once data is written to the FLSWDATA by the software, the DONE bit in the
FLSWCTL register is cleared and is set after hardware writes it to the Flash.
bus and sets the WRDONE bit in the FLSWCTL register indicating that the entire
burst has completed.
8.0.
the MC turn off flow control packet reception on its MAC to
section 8.0
for more details.
82574 GbE Controller—Interconnects
section
8.0.