LFE3-150EA-6FN672I Lattice, LFE3-150EA-6FN672I Datasheet - Page 24
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LFE3-150EA-6FN672I
Manufacturer Part Number
LFE3-150EA-6FN672I
Description
IC FPGA 149KLUTS 380I/O 672FPBGA
Manufacturer
Lattice
Datasheet
1.LFE3-150EA-7FN672C.pdf
(136 pages)
Specifications of LFE3-150EA-6FN672I
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
7014400
Number Of I /o
380
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1100
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE3-150EA-6FN672I
Manufacturer:
LATTICE
Quantity:
3
Company:
Part Number:
LFE3-150EA-6FN672I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Company:
Part Number:
LFE3-150EA-6FN672ITW
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
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Lattice Semiconductor
This allows designers to use highly parallel implementations of DSP functions. Designers can optimize DSP perfor-
mance vs. area by choosing appropriate levels of parallelism. Figure 2-23 compares the fully serial implementation
to the mixed parallel and serial implementation.
Figure 2-23. Comparison of General DSP and LatticeECP3 Approaches
LatticeECP3 sysDSP Slice Architecture Features
The LatticeECP3 sysDSP Slice has been significantly enhanced to provide functions needed for advanced pro-
cessing applications. These enhancements provide improved flexibility and resource utilization.
The LatticeECP3 sysDSP Slice supports many functions that include the following:
• Multiply (one 18x36, two 18x18 or four 9x9 Multiplies per Slice)
• Multiply (36x36 by cascading across two sysDSP slices)
• Multiply Accumulate (up to 18x36 Multipliers feeding an Accumulator that can have up to 54-bit resolution)
• Two Multiplies feeding one Accumulate per cycle for increased processing with lower latency (two 18x18 Mul-
• Flexible saturation and rounding options to satisfy a diverse set of applications situations
• Flexible cascading across DSP slices
• Flexible and Powerful Arithmetic Logic Unit (ALU) Supports:
tiplies feed into an accumulator that can accumulate up to 52 bits)
– Minimizes fabric use for common DSP and ALU functions
– Enables implementation of FIR Filter or similar structures using dedicated sysDSP slice resources only
– Provides matching pipeline registers
– Can be configured to continue cascading from one row of sysDSP slices to another for longer cascade
– Dynamically selectable ALU OPCODE
– Ternary arithmetic (addition/subtraction of three inputs)
– Bit-wise two-input logic operations (AND, OR, NAND, NOR, XOR and XNOR)
– Eight flexible and programmable ALU flags that can be used for multiple pattern detection scenarios, such
chains
Accumulator
Multiplier
Single
Function Implemented in
Operand
General Purpose DSP
A
x
Operand
B
M loops
Multiplier
Operand
0
A
x
Operand
B
2-21
Multiplier
Operand
1
A
accumulate
Function Implemented in
x
(k adds)
m/k
Operand
LatticeECP3
B
+ +
Output
LatticeECP3 Family Data Sheet
Operand
A
x
Multiplier
Operand
B
k
loops
m/k
Architecture