LFE3-150EA-6FN672I Lattice, LFE3-150EA-6FN672I Datasheet - Page 93
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LFE3-150EA-6FN672I
Manufacturer Part Number
LFE3-150EA-6FN672I
Description
IC FPGA 149KLUTS 380I/O 672FPBGA
Manufacturer
Lattice
Datasheet
1.LFE3-150EA-7FN672C.pdf
(136 pages)
Specifications of LFE3-150EA-6FN672I
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
7014400
Number Of I /o
380
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1100
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE3-150EA-6FN672I
Manufacturer:
LATTICE
Quantity:
3
Company:
Part Number:
LFE3-150EA-6FN672I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Company:
Part Number:
LFE3-150EA-6FN672ITW
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
SERDES High Speed Data Receiver
Table 3-9. Serial Input Data Specifications
Input Data Jitter Tolerance
A receiver’s ability to tolerate incoming signal jitter is very dependent on jitter type. High speed serial interface stan-
dards have recognized the dependency on jitter type and have specifications to indicate tolerance levels for differ-
ent jitter types as they relate to specific protocols. Sinusoidal jitter is considered to be a worst case jitter type.
Table 3-10. Receiver Total Jitter Tolerance Specification
RX-CID
V
V
V
V
T
Z
RL
1. This is the number of bits allowed without a transition on the incoming data stream when using DC coupling.
2. This is the typical number of bit times to re-lock to a new phase or frequency within +/- 300 ppm, assuming 8b10b encoded data.
3. AC coupling is used to interface to LVPECL and LVDS. LVDS interfaces are found in laser drivers and Fibre Channel equipment. LVDS inter-
4. Up to 1.76V.
Deterministic
Random
Total
Deterministic
Random
Total
Deterministic
Random
Total
Deterministic
Random
Total
Note: Values are measured with CJPAT, all channels operating, FPGA Logic active, I/Os around SERDES pins quiet, voltages are nominal,
room temperature.
RX-RELOCK
RX-TERM
RX-DIFF-S
RX-IN
RX-CM-DC
RX-CM-AC
Symbol
faces are generally found in 622 Mbps SERDES devices.
RX-RL
Description
S
Stream of nontransitions
(CID = Consecutive Identical Digits) @ 10
Differential input sensitivity
Input levels
Input common mode range (DC coupled)
Input common mode range (AC coupled)
SCDR re-lock time
Input termination 50/75 Ohm/High Z
Return loss (without package)
3.125 Gbps
2.5 Gbps
1.25 Gbps
622 Mbps
Frequency
2
600 mV differential eye
600 mV differential eye
600 mV differential eye
600 mV differential eye
600 mV differential eye
600 mV differential eye
600 mV differential eye
600 mV differential eye
600 mV differential eye
600 mV differential eye
600 mV differential eye
600 mV differential eye
1
Description
Condition
3
-12
BER
3-40
3.125G
2.5G
1.485G
622M
270M
150M
Min.
—
—
—
—
—
—
—
—
—
—
—
—
DC and Switching Characteristics
-20%
Min.
150
0.6
0.1
10
—
—
—
—
—
—
—
0
LatticeECP3 Family Data Sheet
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
50/75/HiZ
1000
Typ.
—
—
—
—
—
—
—
—
—
—
—
Max.
0.47
0.18
0.65
0.47
0.18
0.65
0.47
0.18
0.65
0.47
0.18
0.65
V
V
CCA
CCA
+20%
V
Max.
1760
136
144
160
204
228
296
CCA
—
—
+0.5
+0.2
4
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
Units
mV, p-p
Ohms
Units
Bits
Bits
dB
V
V
V