LFE3-150EA-6FN672I Lattice, LFE3-150EA-6FN672I Datasheet - Page 70
LFE3-150EA-6FN672I
Manufacturer Part Number
LFE3-150EA-6FN672I
Description
IC FPGA 149KLUTS 380I/O 672FPBGA
Manufacturer
Lattice
Datasheet
1.LFE3-150EA-7FN672C.pdf
(136 pages)
Specifications of LFE3-150EA-6FN672I
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
7014400
Number Of I /o
380
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1100
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE3-150EA-6FN672I
Manufacturer:
LATTICE
Quantity:
3
Company:
Part Number:
LFE3-150EA-6FN672I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Company:
Part Number:
LFE3-150EA-6FN672ITW
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
LatticeECP3 External Switching Characteristics (Continued)
t
t
f
t
t
t
t
t
f
t
t
t
t
t
f
t
t
t
t
t
f
General I/O Pin Parameters Using Dedicated Clock Input Primary Clock with PLL with Clock Injection Removal
Setting
t
t
SU_DEL
H_DEL
MAX_IO
CO
SU
H
SU_DEL
H_DEL
MAX_IO
CO
SU
H
SU_DEL
H_DEL
MAX_IO
CO
SU
H
SU_DEL
H_DEL
MAX_IO
COPLL
SUPLL
Parameter
2
Clock to Data Setup - PIO Input
Register with Data Input Delay
Clock to Data Hold - PIO Input
Register with Input Data Delay
Clock Frequency of I/O and PFU
Register
Clock to Output - PIO Output
Register
Clock to Data Setup - PIO Input
Register
Clock to Data Hold - PIO Input
Register
Clock to Data Setup - PIO Input
Register with Data Input Delay
Clock to Data Hold - PIO Input
Register with Input Data Delay
Clock Frequency of I/O and PFU
Register
Clock to Output - PIO Output
Register
Clock to Data Setup - PIO Input
Register
Clock to Data Hold - PIO Input
Register
Clock to Data Setup - PIO Input
Register with Data Input Delay
Clock to Data Hold - PIO Input
Register with Input Data Delay
Clock Frequency of I/O and PFU
Register
Clock to Output - PIO Output
Register
Clock to Data Setup - PIO Input
Register
Clock to Data Hold - PIO Input
Register
Clock to Data Setup - PIO Input
Register with Data Input Delay
Clock to Data Hold - PIO Input
Register with Input Data Delay
Clock Frequency of I/O and PFU
Register
Clock to Output - PIO Output
Register
Clock to Data Setup - PIO Input
Register
Over Recommended Commercial Operating Conditions
Description
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
ECP3-150EA
ECP3-150EA
3-17
Device
DC and Switching Characteristics
Min. Max. Min. Max. Min. Max.
1.3
0.0
0.0
1.4
1.3
0.0
0.0
1.2
1.3
0.0
0.0
1.3
1.3
0.0
0.7
—
—
—
—
—
—
—
—
LatticeECP3 Family Data Sheet
-8
500
500
500
500
3.8
3.7
2.4
3.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.5
0.0
0.0
1.6
1.5
0.0
0.0
1.4
1.4
0.0
0.0
1.5
1.4
0.0
0.8
—
—
—
—
—
—
—
—
-7
1, 2
420
420
420
420
4.2
4.1
3.9
2.6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.7
0.0
0.0
1.8
1.7
0.0
0.0
1.6
1.5
0.0
0.0
1.6
1.5
0.0
0.9
—
—
—
—
—
—
—
—
-6
375
375
375
375
4.6
4.5
4.3
2.9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns