PIC16F1526-I/PT Microchip Technology, PIC16F1526-I/PT Datasheet - Page 105

MCU 14KB FLASH 768B RAM 64-TQFP

PIC16F1526-I/PT

Manufacturer Part Number
PIC16F1526-I/PT
Description
MCU 14KB FLASH 768B RAM 64-TQFP
Manufacturer
Microchip Technology
Datasheet

Specifications of PIC16F1526-I/PT

Processor Series
PIC16F
Core
PIC
Program Memory Type
Flash
Program Memory Size
14 KB
Data Ram Size
768 B
Interface Type
MI2C, SPI, EUSART
Number Of Timers
9
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TQFP-64
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F1526-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC16F1526-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
11.2.3
While executing code, program memory can only be
erased by rows. To erase a row:
1.
2.
3.
4.
5.
See
After the “BSF PMCON1,WR” instruction, the processor
requires two cycles to set up the erase operation. The
user must place two NOP instructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms erase time. This is not Sleep mode as the
clocks and peripherals will continue to run. After the
erase cycle, the processor will resume operation with
the third instruction after the PMCON1 WRITE instruc-
tion.
 2011 Microchip Technology Inc.
Load the PMADRH:PMADRL register pair with
any address within the row to be erased.
Clear the CFGS bit of the PMCON1 register.
Set the FREE and WREN bits of the PMCON1
register.
Write 55h, then AAh, to PMCON2 (Flash
programming unlock sequence).
Set control bit WR of the PMCON1 register to
begin the erase operation.
Example
ERASING FLASH PROGRAM
MEMORY
12-2.
Preliminary
FIGURE 11-4:
PIC16(L)F1526/27
Program or Configuration Memory
Disable Write/Erase Operation
Enable Write/Erase Operation
Erase operation completes
Select Erase Operation
(PMADRH:PMADRL)
Re-enable Interrupts
Select Row Address
Disable Interrupts
Unlock Sequence
Erase Operation
CPU stalls while
Erase Operation
(FIGURE x-x)
(2ms typical)
(WREN = 1)
(WREN = 0)
FLASH PROGRAM
MEMORY ERASE
FLOWCHART
(FREE = 1)
Figure 11-3
(GIE = 0)
(GIE = 1)
(CFGS)
Select
Start
End
DS41458A-page 105

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