ICS953002CFLFT IDT, Integrated Device Technology Inc, ICS953002CFLFT Datasheet - Page 24

• Manufacturer Part Number: ICS953002CFLFT
• Description: IC TIMING CTRL HUB P4 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr

Specifications of ICS953002CFLFT

• Input: Clock
• Output: Clock
• Frequency - Max: 66MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Frequency-max: 66MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 953002CFLFT

0924—11/18/09
I
I
I
I
2
2
2
2
C Table: Byte Count Register
C Table: WD Time Control Register
C Table: M/N Programming & WD Safe Frequency Control Register
C Table: PLL1 Frequency Control Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 10
Byte 11
Byte 8
Byte 9
Integrated
Circuit
Systems, Inc.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pin #
Pin #
Pin #
Pin #
WD Alarm Status
WD Soft Status
WD Safe Freq
Reserved
Reserved
WDTCtrl
WD SF4
WD SF3
WD SF2
WD SF1
WD SF0
WDSEN
Source
WDEN
N Div8
N Div9
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
Name
Name
Name
Name
WD2
WD1
WD0
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Watch Dog Time base
WD Soft Reset Status
WD Safe Freq Source
Watch Dog Safe Freq
Watchdog Soft Reset
Programming b(7:0)
N Divider Prog bit 8
N Divider Prog bit 9
Control Function
Control Function
Control Function
Control Function
Watchdog Enable
Programming bits
Programming bits
WD Alarm Status
WD Timer Bit 2
WD Timer Bit 1
WD Timer Bit 0
Byte Count
Reserved
Reserved
M Divider
Control
Enable
24
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
VCO Frequency = 14.318 x [NDiv(9:0)+8]
the watchdog timer waits before it goes to
These bits represent X*290ms (or 1.16S)
Divier in Byte 11 and 12 will configure the
Writing to these bit will configure the safe
Writing to this register will configure how
alarm mode. Default is 7 X 290ms = 2s.
PLL1 VCO frequency. Default at power
many bytes will be read back, default is
The decimal representation of M and N
290ms Base
up = latch-in or Byte 0 Rom table.
B10b(4:0)
Disable
Disable
Normal
Normal
frequency as Byte0 bit (4:0).
0
0
0
0
-
-
/ [MDiv(5:0)+2]
0F = 15 bytes.
1160ms Base
Latch Inputs
Enable
Enable
Alarm
Alarm
1
1
1
1
-
-
ICS953002
PWD
PWD
PWD
PWD
0
0
0
0
1
1
1
1
0
0
x
x
0
1
1
1
1
1
0
0
0
0
0
0
X
X
X
X
X
X
X
X