ICS953002CFLFT IDT, Integrated Device Technology Inc, ICS953002CFLFT Datasheet - Page 29

• Manufacturer Part Number: ICS953002CFLFT
• Description: IC TIMING CTRL HUB P4 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr

Specifications of ICS953002CFLFT

• Input: Clock
• Output: Clock
• Frequency - Max: 66MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Frequency-max: 66MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 953002CFLFT

0924—11/18/09
1
1
2
Absolute Maximum Rating
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
Electrical Characteristics - Input/Supply/Common Output Parameters
Guaranteed by design and characterization, not 100% tested in production.
Guaranteed by design and characterization, not 100% tested in production.
Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
Input ESD protection HBM
3.3V Core Supply Voltage
Ambient Operating Temp
Operating Supply Current
Low-level Output Voltage
3.3V Logic Input Supply
Modulation Frequency
Storage Temperature
Clock/Data Rise Time
Low Threshold Input-
Low Threshold Input-
Clock/Data Fall Time
Powerdown Current
Case Temperature
Input High Current
Input High Voltage
Input Low Current
Operating Current
Input Capacitance
Input Low Voltage
Current sinking at
Input Frequency
Clk Stabilization
Pin Inductance
SMBus Voltage
PARAMETER
PARAMETER
SCLK/SDATA
SCLK/SDATA
High Voltage
Low Voltage
Tdrive_PD#
Integrated
Circuit
Systems, Inc.
V
Trise_Pd#
Tfall_Pd#
Voltage
OL
= 0.4 V
SYMBOL
Tambient
ESD prot
SYMBOL
VDD_In
VDD_A
Tcase
I
I
I
I
V
DD3.3OP
DD3.3OP
DD3.3PD
V
T
PULLUP
C
T
T
C
Ts
L
C
V
V
V
V
I
I
IH_FS
IL_FS
STAB
I
F
IL1
IL2
RI2C
FI2C
OUT
IH
pin
INX
DD
OL
IH
IL
IN
i
V
assertion of PD# to 1st clock
IN
V
all differential pairs tri-stated
From V
Full Active, C
IN
= 0 V; Inputs with no pull-up
CPU output enable after
Output pin capacitance
Triangular Modulation
= 0 V; Inputs with pull-up
(Max VIL - 0.15) to
(Min VIH + 0.15) to
all diff pairs driven
PD# de-assertion
all outputs driven
(Min VIH + 0.15)
(Max VIL - 0.15)
PD# rise time of
CONDITIONS*
CONDITIONS
PD# fall time of
X1 & X2 pins
Logic Inputs
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
DD
V
V
resistors
@ I
resistors
DD
Power-Up or de-
IN
= 3.3 V
= V
PULLUP
-
-
-
-
-
-
L
= Full load;
DD
29
GND - 0.5
V
V
SS
SS
2000
MIN
-200
MIN
-65
0.7
2.7
30
-5
-5
0
2
4
- 0.3
- 0.3
14.31818
TYP
TYP
V
V
V
V
DD
DD
DD
DD
MAX
MAX
1000
0.35
150
115
350
400
300
300
0.8
1.8
+ 0.5V
+ 0.5V
70
5.5
0.4
70
12
33
+ 0.3
5
+ 0.3
7
5
6
5
5
5
UNITS
UNITS
ICS953002
MHz
kHz
mA
mA
mA
mA
ms
mA
°
°C
°C
uA
uA
uA
nH
pF
pF
pF
us
ns
ns
ns
ns
V
V
V
C
V
V
V
V
V
V
Notes
Notes
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1