ICS953002CFLFT IDT, Integrated Device Technology Inc, ICS953002CFLFT Datasheet - Page 25

• Manufacturer Part Number: ICS953002CFLFT
• Description: IC TIMING CTRL HUB P4 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr

Specifications of ICS953002CFLFT

• Input: Clock
• Output: Clock
• Frequency - Max: 66MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Frequency-max: 66MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 953002CFLFT

0924—11/18/09
I
I
I
I
2
2
2
2
C Table: PLL1 Frequency Control Register
C Table: PLL1 Spread Spectrum Control Register
C Table: PLL1 Spread Spectrum Control Register
C Table: Output Divider Control Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 12
Byte 13
Byte 14
Byte 15
Integrated
Circuit
Systems, Inc.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pin #
Pin #
Pin #
Pin #
AGP/PCIDiv3
AGP/PCIDiv2
AGP/PCIDiv1
AGP/PCIDiv0
Reserved
CPUDiv3
CPUDiv2
CPUDiv1
CPUDiv0
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
SSP14
SSP13
SSP12
SSP11
SSP10
Name
Name
Name
Name
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
SSP9
SSP8
N Divider Programming
AGP/PCI Divider Ratio
Programming b(14:8)
Programming b(7:0)
Programmaing Bits
Control Function
Control Function
Control Function
Control Function
Programmaing Bits
CPU Divider Ratio
Spread Spectrum
Spread Spectrum
Reserved
b(7:0)
PLL2
25
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
VCO Frequency = 14.318 x [NDiv(9:0)+8]
and 14 will program the spread pecentage
and 14 will program the spread pecentage
Divier in Byte 11 and 12 will configure the
PLL1 VCO frequency. Default at power
0000:/2
0001:/3
0010:/5
0011:/7
0000:/2
0001:/3
0010:/5
0011:/7
The decimal representation of M and N
These Spread Spectrum bits in Byte 13
These Spread Spectrum bits in Byte 13
up = latch-in or Byte 0 Rom table.
0
0
0
0
-
0110:/10 1010:/20 1110:/40
0111:/14 1011:/28 1111:/56
0110:/10 1010:/20 1110:/40
0111:/14 1011:/28 1111:/56
0100:/4
0101:/6
0100:/4
0101:/6
/ [MDiv(5:0)+2]
of PLL1
of PLL1
1001:/12 1101:/24
1001:/12 1101:/24
1000:/8
1000:/8
1
1
1
1
-
1100:/16
1100:/16
ICS953002
PWD
PWD
PWD
PWD
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X