ICS9LPRS511EGLF IDT, Integrated Device Technology Inc, ICS9LPRS511EGLF Datasheet - Page 10

• Manufacturer Part Number: ICS9LPRS511EGLF
• Description: IC TIMING CTRL HUB P4 64-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr

Specifications of ICS9LPRS511EGLF

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9LPRS511EGLF

1137—09/05/08
I2C Table: WD Safe Frequency Control Register
I
I2C Table: CPU PLL Frequency Control Register (DOC0 = 0)
I2C Table: CPU PLL Spread Spectrum Control Register
I2C Table: CPU PLL Spread Spectrum Control Register
Byte 10
Byte 11
Byte 12
Byte 13
Byte 14
2
C Table: CPU PLL Frequency Control Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Integrated
Circuit
Systems, Inc.
WD SF4
WD SF3
WD SF2
WD SF1
WD SF0
N Div10
N Div2
N Div1
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
N Div9
N Div8
N Div7
N Div6
N Div5
N Div4
N Div3
SSP15
SSP14
SSP13
SSP12
SSP11
SSP10
SWD2
SWD1
SWD0
Name
Name
Name
Name
Name
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
SSP9
SSP8
Byte12 bit(7:0) and Byte11
WD Soft Alarm Timer Bit 2
WD Soft Alarm Timer Bit 1
WD Soft Alarm Timer Bit 0
M Divider Programming
N Divider Programming
Programming bit(14:8)
Watch Dog Safe Freq
Programming bit(7:0)
N Divider Prog bit 2
N Divider Prog bit 1
Control Function
Control Function
Control Function
Control Function
Control Function
Programming bits
Spread Spectrum
Spread Spectrum
bit (5:0)
bit(7:6)
Type
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
These bits represent X*290ms (or 1.16S) the watchdog timer
at power up = latch-in or Byte 0 Rom table. VCO Frequency
at power up = latch-in or Byte 0 Rom table. VCO Frequency
These Spread Spectrum bits in Byte 13 and 14 will program
These Spread Spectrum bits in Byte 13 and 14 will program
and 12 will configure the CPU PLL VCO frequency. Default
and 12 will configure the CPU PLL VCO frequency. Default
waits before it goes to alarm mode. Default is 7 X 290ms =
The decimal representation of M and N Divider in Byte 11
The decimal representation of M and N Divider in Byte 11
Writing to these bit will configure the safe frequency as
10
the spread percentage of CPU PLL
the spread percentage of CPU PLL
0
0
0
0
0
= 14.318 x Ndiv(10:0)/Mdiv(5:0)
= 14.318 x Ndiv(10:0)/Mdiv(5:0)
Byte10 bit (4:0).
2s.
1
1
1
1
1
Advance Information
A/B/C/D/E/H/J
A/B/C/D/E/H/J
A/B/C/D/E/H/J
A/B/C/D/E/H/J
A/B/C/D/E/H/J
ICS9LPRS511
PWD
PWD
PWD
PWD
PWD
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
0
0
0
0
0
0