ICS9LPRS511EGLF IDT, Integrated Device Technology Inc, ICS9LPRS511EGLF Datasheet - Page 9

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ICS9LPRS511EGLF

Manufacturer Part Number
ICS9LPRS511EGLF
Description
IC TIMING CTRL HUB P4 64-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Timing Control Hubr
Datasheet

Specifications of ICS9LPRS511EGLF

Input
Crystal
Output
Clock
Frequency - Max
400MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TSSOP
Frequency-max
400MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
9LPRS511EGLF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS9LPRS511EGLFT
Manufacturer:
IDT
Quantity:
20 000
1137—09/05/08
I2C Table: Output Control Register
I2C Table: Reserved Register
I2C Table: Revision and Vendor ID Register
I2C Table: Byte Count Register
I2C Table: Watch Dog Timer Control Register
Byte 7
Byte 5
Byte 6
Byte 8
Byte 9
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
applicable to revisions
this is a reserved bit)
H and J, otherwise
WD Hard Status
Integrated
Circuit
Systems, Inc.
WD Soft Status
iAMT EN (only
Load Control
24_48Mhz
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
HWD_EN
SWD_EN
Diff AMP
Diff AMP
WDTCtrl
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
HWD2
HWD1
HWD0
Name
Name
Name
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
WD Hard Alarm Timer Bit 2
WD Hard Alarm Timer Bit 1
WD Hard Alarm Timer Bit 0
Byte Count Programming
Control Function
Watch Dog Alarm Time
WD Hard Alarm Status
Watchdog Hard Alarm
WD Soft Alarm Status
Watchdog Soft Alarm
iAMT Enable Control
Control Function
Control Function
Control Function
Control Function
Amplitude Control
VENDOR ID
Differential output
Revision ID
IIC Load control
Output Control
base Control
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Enable
Enable
b(7:0)
Type
R
R
R
R
R
R
R
R
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
These bits represent X*290ms (or 1.16S) the watchdog timer
Writing to this register will configure how many bytes will be
waits before it goes to alarm mode. Default is 7 X 290ms =
001 = ICS
290ms Base
00 = 600mV
10 = 800mV
0
-
-
-
-
-
-
-
Stoppable
Disable
Disable
Disable
Normal
Normal
Load
read back, default is 0F = 15 bytes.
9
0
0
0
0
-
-
-
-
-
-
-
-
-
-
2s.
1
-
-
-
-
-
-
-
-
1160ms Base
Free-running
01 = 900mV
11 = 700mV
Do not Load
Enable
Enable
Enable
Alarm
Alarm
1
1
1
1
-
-
-
-
-
-
-
-
-
-
-
Advance Information
PWD
A/B
0
0
0
0
0
0
0
1
A/B/C/D/E/H/J
A/B/C/D/E/H/J
A/B/C/D/E/H/J
A/B/C/D/E/H/J
PWD
PWD
PWD
PWD
ICS9LPRS511
X
X
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
PWD
C/D
0
0
1
0
0
0
0
1
PWD
E
0
1
0
0
0
0
0
1
PWD
H
0
1
0
1
0
0
0
1
PWD
J
0
1
1
0
0
0
0
1

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