ICS9LPRS511EGLF IDT, Integrated Device Technology Inc, ICS9LPRS511EGLF Datasheet - Page 11

• Manufacturer Part Number: ICS9LPRS511EGLF
• Description: IC TIMING CTRL HUB P4 64-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr

Specifications of ICS9LPRS511EGLF

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9LPRS511EGLF

1137—09/05/08
I2C Table: PCIEX PLL Frequency Control Register
I2C Table: PCIEX PLL Frequency Control Register (DOC0 = 0)
I2C Table: PCIEX PLL Spread Spectrum Control Register
I2C Table: PCIEX PLL Spread Spectrum Control Register
I2C Table: PCIEX PLL Frequency Select Register
Byte 15
Byte 16
Byte 17
Byte 18
Byte 19
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Integrated
Circuit
Systems, Inc.
Reserved
Reserved
Reserved
N Div10
N Div2
N Div1
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
N Div9
N Div8
N Div7
N Div6
N Div5
N Div4
N Div3
SSP15
SSP14
SSP13
SSP12
SSP11
SSP10
Name
Name
Name
Name
Name
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
SSP9
SSP8
FSLC
FSLB
FSLA
FS4
FS3
Byte16 bit(7:0) and Byte15
M Divider Programming
N Divider Programming
Programming bit(14:8)
Programming bit(7:0)
N Divider Prog bit 2
N Divider Prog bit 1
Control Function
Control Function
Control Function
Control Function
Control Function
Spread Spectrum
Spread Spectrum
Freq Select Bit 4
Freq Select Bit 3
Freq Select Bit 2
Freq Select Bit 1
Freq Select Bit 0
Reserved
Reserved
Reserved
bit (5:0)
bit(7:6)
Type
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
and 16 will configure the PCIEX PLL VCO frequency. Default
and 16 will configure the PCIEX PLL VCO frequency. Default
at power up = latch-in or Byte 0 Rom table. VCO Frequency
at power up = latch-in or Byte 0 Rom table. VCO Frequency
These Spread Spectrum bits in Byte 17 and 18 will program
These Spread Spectrum bits in Byte 17 and 18 will program
The decimal representation of M and N Divider in Byte 15
The decimal representation of M and N Divider in Byte 15
See Table 2: PCIEX PLL Frequency Selection Table
11
the spread percentage of PCIEX PLL
the spread percentage of PCIEX PLL
0
0
0
0
0
-
-
-
= 14.318 x Ndiv(10:0)/Mdiv(5:0)
= 14.318 x Ndiv(10:0)/Mdiv(5:0)
1
1
1
1
1
-
-
-
Advance Information
A/B/C/D/E/H/J
A/B/C/D/E/H/J
A/B/C/D/E/H/J
A/B/C/D/E/H/J
A/B/C/D/E/H/J
ICS9LPRS511
Latch
Latch
Latch
PWD
PWD
PWD
PWD
PWD
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
0
0
0