ICS9LPRS511EGLF IDT, Integrated Device Technology Inc, ICS9LPRS511EGLF Datasheet - Page 12

• Manufacturer Part Number: ICS9LPRS511EGLF
• Description: IC TIMING CTRL HUB P4 64-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr

Specifications of ICS9LPRS511EGLF

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9LPRS511EGLF

1137—09/05/08
I2C Table: Output Control Register
I2C Table: Synchronization Control Register
I2C Table: DOC pin control register
I2C Table: CPU PLL DOC 1 N programming Register (DOC0 = 1)
Bytes 24 and 25 are reserved
I2C Table: PCIEX PLL DOC 1 N programming Register (DOC0 = 1)
Byte 20
Byte 21
Byte 22
Byte 23
Byte 26
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Integrated
Circuit
Systems, Inc.
PCIEX PLL TBEN
PCIEX Source
SATA Source
CPU PLL TBEN
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RESET Sync
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
N Div10
N Div10
N Div9
N Div8
N Div7
N Div6
N Div5
N Div4
N Div3
N Div9
N Div8
N Div7
N Div6
N Div5
N Div4
N Div3
PCIEX
Name
Name
Name
Name
Reserved
Reserved
Reserved
Reserved
Reserved
CPU
Name
Byte23 bit(7:0) and Byte11
Byte26 bit(7:0) and Byte15
N Divider Programming
N Divider Programming
PCIEX PLL DOC0 pin
CPU PLL DOC0 pin
Control Function
Control Function
Control Function
Control Function
PCIEX PLL Turbo Enable
CPU PLL Turbo Enable
PCIEX Source
Reset Synchronization
SATA Source
upon Reset (Byte 21)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
control
control
bit(7:6)
bit(7:6)
Reserved
Reserved
Reserved
Reserved
Reserved
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
RW
RW
RW
RW
RW
RW
RW
RW
and 26 will configure the PCIEX PLL VCO frequency. VCO
The decimal representation of M and N Divider in Byte 11
and 23 will configure the CPU PLL VCO frequency. VCO
The decimal representation of M and N Divider in Byte 15
Frequency = 14.318 x Ndiv(10:0)/Mdiv(5:0)
PCIEX PLL
PCIEX PLL
Frequency = 14.318 x Ndiv(10:0)/Mdiv(5:0)
12
Enabled
Enabled
0
-
-
-
-
-
-
0
0
0
-
-
-
-
-
-
Disable
Disable
Disable
0
-
-
-
-
-
Fixed PLL
CPU PLL
Disabled
Disabled
1
-
-
-
-
-
-
1
1
1
-
-
-
-
-
-
Advance Information
Enable
Enable
Enable
1
-
-
-
-
-
A/B/C/D/E/H/J
A/B/C/D/E/H/J
A/B/C/D/E/H/J
ICS9LPRS511
PWD
A/B
PWD
PWD
PWD
0
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
0
0
0
0
1
1
A/B/C/D/E/H/J
C/D/E/H
PWD
1
1
1
1
1
1
1
1
PWD
0
0
0
0
0
0
0
0
PWD
0
1
1
1
1
1
1
1
J