SI5319C-C-GMR Silicon Laboratories Inc, SI5319C-C-GMR Datasheet - Page 11

• Manufacturer Part Number: SI5319C-C-GMR
• Description: IC CLOCK MULT/ATTENUATOR 36QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5319C-C-GMR

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 36-VFQFN Exposed Pad
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 4. AC Specifications (Continued)
(V
LVCMOS Output Pins
Rise/Fall Times
LOSn Trigger Window
Time to Clear LOL
after LOS Cleared
Device Skew
Input to Output Phase
Change Due to Tem-
perature Variation
PLL Performance
(fin=fout = 622.08 MHz; BW=120 Hz; LVPECL)
Lock Time
Output Clock Phase
Change
Closed Loop Jitter
Peaking
Jitter Tolerance
Subharmonic Noise
Spurious Noise
Phase Noise
fout = 622.08 MHz
DD
= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T
Parameter
LOS
Symbol
t
SP
SP
t
t
CKO
LOCKMP
CLRLOL
P_STEP
t
J
TEMP
J
t
TOL
SUBH
SPUR
RF
PK
TRIG
PN
Internal detection of LOSn
(n  1, n x F3 < 100 MHz)
Max phase changes from
Start of ICAL to of LOL
Phase Noise @ 100 kHz
Jitter Frequency Loop
A
Stable Xa/XB reference
From last CKINn to 
= –40 to 85 °C)
Max spur @ n x F3
After clock switch
Test Condition
LOS to LOL
100 kHz Offset
–40 to +85 °C
10 kHz Offset
C
See Figure 2
1 MHz Offset
f3  128 kHz
Fold = Fnew
1 kHz Offset
Bandwidth
LOAD
N3 ≠ 1
Offset
= 20pf
Rev. 1.0
5000/BW
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
–121
–106
–132
–132
0.05
Typ
300
200
–88
–93
25
10
35
—
—
4.5 x N3
1200
–100
–104
–119
Max
500
–87
–76
–70
0.1
—
—
—
—
Si5319
ns pk-pk
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
T
Unit
dBc
dBc
CKIN
ms
ms
dB
ns
ps
ps
11