ICS854104AGLF IDT, Integrated Device Technology Inc, ICS854104AGLF Datasheet - Page 5
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ICS854104AGLF
Manufacturer Part Number
ICS854104AGLF
Description
IC FANOUT BUFF DIFF-LVDS 16TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Fanout Buffer (Distribution)r
Datasheet
1.ICS854104AGLF.pdf
(15 pages)
Specifications of ICS854104AGLF
Number Of Circuits
1
Ratio - Input:output
1:4
Differential - Input:output
Yes/Yes
Input
HCSL, LVDS, LVHSTL, LVPECL, SSTL
Output
LVDS
Frequency - Max
700MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Frequency-max
700MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
800-1183
800-1183-5
800-1183
854104AGLF
800-1183-5
800-1183
854104AGLF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICS854104AGLF
Manufacturer:
Microchip
Quantity:
343
ICS854104 Data Sheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
ICS854104AG REVISION A AUGUST 14, 2009
Offset from Carrier Frequency (Hz)
5
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Additive Phase Jitter @ 155.52MHz
12kHz to 20MHz = 0.232ps (typical)
©2009 Integrated Device Technology, Inc.