ICS854104AGLF IDT, Integrated Device Technology Inc, ICS854104AGLF Datasheet - Page 9

• Manufacturer Part Number: ICS854104AGLF
• Description: IC FANOUT BUFF DIFF-LVDS 16TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution)r

Specifications of ICS854104AGLF

• Number Of Circuits: 1
• Ratio - Input:output: 1:4
• Differential - Input:output: Yes/Yes
• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVDS
• Frequency - Max: 700MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 700MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1183; 800-1183-5; 800-1183; 854104AGLF

ICS854104 Data Sheet
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both signals must meet the V
input requirements. Figures 2A to 2F show interface examples for the
HiPerClockS CLK/nCLK input driven by the most common driver
types. The input interfaces suggested here are examples only.
2A. HiPerClockS CLK/nCLK Input Driven by an IDT
Figure 3C. HiPerClockS CLK/nCLK Input
Figure 2E. HiPerClockS CLK/nCLK Input
ICS854104AG REVISION A AUGUST 14, 2009
Open Emitter HiPerClockS LVHSTL Driver
2.5V
1.8V
3.3V
HCSL
LVPECL
*Optional – R3 and R4 can be 0Ω
LVHSTL
IDT
HiPerClockS
LVHSTL Driver
Driven by a 3.3V LVPECL Driver
Driven by a 3.3V HCSL Driver
*R3
*R4
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
33
33
Zo = 50Ω
Zo = 50Ω
R3
125
R1
50
3.3V
R1
84
R1
50
R4
125
R2
50
R2
84
R2
50
CLK
nCLK
CLK
nCLK
CLK
nCLK
3.3V
3.3V
3.3V
HiPerClockS
Input
HiPerClockS
Input
HiPerClockS
Input
PP
and V
CMR
9
Please consult with the vendor of the driver component to confirm the
driver termination requirements. For example, in Figure 2A, the input
termination applies for IDT HiPerClockS open emitter LVHSTL
drivers. If you are using an LVHSTL driver from another vendor, use
their termination recommendation.
Figure 2B. HiPerClockS CLK/nCLK Input
Figure 2D. HiPerClockS CLK/nCLK Input
Figure 2F. HiPerClockS CLK/nCLK Input
2.5V
3.3V
3.3V
SSTL
LVDS
LVPECL
Driven by a 3.3V LVPECL Driver
Driven by a 3.3V LVDS Driver
Driven by a 2.5V SSTL Driver
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Zo = 60Ω
Zo = 60Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
R3
120
2.5V
R1
120
R1
50
©2009 Integrated Device Technology, Inc.
R2
50
R4
120
R2
120
R2
50
R1
100
CLK
nCLK
CLK
nCLK
CLK
nCLK
3.3V
3.3V
HiPerClockS
3.3V
HiPerClockS
Input
Receiver