AD9512BCPZ Analog Devices Inc, AD9512BCPZ Datasheet - Page 41

• Manufacturer Part Number: AD9512BCPZ
• Description: IC CLOCK DIST 5OUT PLL 48LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Dividerr

Specifications of AD9512BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 5
• No. Of Multipliers / Dividers: 5
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9512/PCB - BOARD EVAL CLOCK 5CHAN 48LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Reg.
Addr.
(Hex)
45
45
45
45
45
45
46 (47)
(48) (49)
4A
(4C)
(4E)
(50)
(52)
4A
(4C)
(4E)
(50)
(52)
4B
(4D)
(4F)
(51)
(53)
4B
(4D)
(4F)
(51)
(53)
4B
(4D)
(4F)
(51)
(53)
4B
(4D)
(4F)
(51)
(53)
Bit(s)
<0>
<1>
<2>
<4:3>
<5>
<7:6>
<7:0>
<3:0>
<7:4>
<3:0>
<4>
<5>
<6>
Name
CLK1 AND CLK2
Clock Select
CLK1 Power-Down
CLK2 Power-Down
All Clock Inputs Power-
Down
DIVIDERS
Divider High
OUT0
(OUT1)
(OUT2)
(OUT3)
(OUT4)
Divider Low
OUT0
(OUT1)
(OUT2)
(OUT3)
(OUT4)
Phase Offset
OUT0
(OUT1)
(OUT2)
(OUT3)
(OUT4)
Start
OUT0
(OUT1)
(OUT2)
(OUT3)
(OUT4)
Force
OUT0
(OUT1)
(OUT2)
(OUT3)
(OUT4)
Nosync
OUT0
(OUT1)
(OUT2)
(OUT3)
(OUT4)
Description
0: CLK2 Drives Distribution Section.
1: CLK1 Drives Distribution Section (Default).
1 = CLK1 Input Is Powered Down (Default = 0b).
1 = CLK2 Input Is Powered Down (Default = 0b).
Not Used.
1 = Power-Down CLK1 and CLK2 Inputs and Associated Bias and Internal Clock Tree;
(Default = 0b).
Not Used.
Not Used.
Number of Clock Cycles Divider Output Stays High.
Number of Clock Cycles Divider Output Stays Low.
Phase Offset (Default = 0000b).
Selects Start High or Start Low.
(Default = 0b).
Forces Individual Outputs to the State Specified in Start (Above).
This Function Requires That Nosync (Below) Also Be Set (Default = 0b).
Ignore Chip-Level Sync Signal (Default = 0b).
Rev. A | Page 41 of 48
AD9512