AD9512BCPZ Analog Devices Inc, AD9512BCPZ Datasheet - Page 43

• Manufacturer Part Number: AD9512BCPZ
• Description: IC CLOCK DIST 5OUT PLL 48LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Dividerr

Specifications of AD9512BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 5
• No. Of Multipliers / Dividers: 5
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9512/PCB - BOARD EVAL CLOCK 5CHAN 48LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

POWER SUPPLY
The AD9512 requires a 3.3 V ± 5% power supply for V
The tables in the Specifications section give the performance
expected from the AD9512 with the power supply voltage
within this range. The absolute maximum range of −0.3 V to
+3.6 V, with respect to GND, must never be exceeded on
the VS pin.
Good engineering practice should be followed in the layout of
power supply traces and ground plane of the PCB. The power
supply should be bypassed on the PCB with adequate
capacitance (>10 μF). The AD9512 should be bypassed with
adequate capacitors (0.1 μF) at all power pins, as close as
possible to the part. The layout of the AD9512 evaluation board
(AD9512/PCB) is a good example.
The AD9512 is a complex part that is programmed for its
desired operating configuration by on-chip registers. These
registers are not maintained over a shutdown of external power.
This means that the registers can lose their programmed values
if V
Careful bypassing should protect the part from memory loss
under normal conditions. Nonetheless, it is important that the
V
losing its programming.
The internal bias currents of the AD9512 are set by the R
resistors. This resistor should be as close as possible to the value
given as conditions in the Specifications section
(R
be readily obtainable. The bias currents set by this resistor
determine the logic levels and operating conditions of the
internal blocks of the AD9512. The performance figures given
in the Specifications section assume that this specific resistor
value is used.
The exposed metal paddle on the AD9512 package is an
electrical connection, as well as a thermal enhancement. For
the device to function properly, the paddle must be properly
attached to ground (GND). The PCB acts as a heat sink for the
AD9512; therefore, this GND connection should provide a
good thermal path to a larger dissipation area, such as a ground
plane on the PCB. See the layout of the AD9512 evaluation
board (AD9512/PCB or AD9512-VCO/PCB) for a good
example.
S
SET
power supply not become intermittent, or the AD9512 risks
S
is lost long enough for the internal voltages to collapse.
= 4.12 kΩ). This is a standard 1% resistor value and should
S
.
SET
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POWER MANAGEMENT
The power usage of the AD9512 can be managed to use only the
power required for the functions that are being used. Unused
features and circuitry can be powered down to save power. The
following circuit blocks can be powered down, or are powered
down when not selected (see the Register Map and Description
section):
•
•
•
•
Powering down a functional block does not cause the
programming information for that block (in the registers) to be
lost. This means that blocks can be powered on and off without
otherwise having to reprogram the AD9512. However,
synchronization is lost. A SYNC must be issued to
resynchronize (see the Single-Chip Synchronization section).
Any of the dividers are powered down when bypassed—
equivalent to divide-by-one.
The adjustable delay block on OUT4 is powered down
when not selected.
Any output can be powered down. However, LVPECL
outputs have both a safe and an off condition. When the
LVPECL output is terminated, only the safe shutdown
should be used to protect the LVPECL output devices. This
still consumes some power.
The entire distribution section can be powered down when
not needed.
AD9512