AD9512BCPZ Analog Devices Inc, AD9512BCPZ Datasheet - Page 42

• Manufacturer Part Number: AD9512BCPZ
• Description: IC CLOCK DIST 5OUT PLL 48LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Dividerr

Specifications of AD9512BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 5
• No. Of Multipliers / Dividers: 5
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9512/PCB - BOARD EVAL CLOCK 5CHAN 48LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9512
Reg.
Addr.
(Hex)
4B
(4D)
(4F)
(51)
(53)
54 (55)
(56) (57)
58
58
58
58
58
58
58
59
5A
5A
END
Bit(s)
<7>
<7:0>
<0>
<1>
<2>
<3>
<4>
<6:5>
<7>
<7:0>
<0>
<7:1>
Name
Bypass Divider
OUT0
(OUT1)
(OUT2)
(OUT3)
(OUT4)
FUNCTION
SYNC Detect Enable
SYNC Select
Soft SYNC
Dist Ref Power-Down
SYNC Power-Down
FUNCTION Pin Select
Update Registers
Description
Bypass and Power-Down Divider Logic; Route Clock Directly to Output (Default = 0b).
Not Used.
1 = Enable SYNC Detect (Default = 0b).
1 = Raise Flag if Slow Clocks Are Out-of-Sync by 0.5 to 1 High Speed Clock Cycles.
0 (Default) = Raise Flag if Slow Clocks Are Out-of-Sync by 1 to 1.5 High Speed Clock Cycles.
Soft SYNC bit works the same as the FUNCTION pin when in SYNCB mode, except that this bit’s
polarity is reversed. That is, a high level forces selected outputs into a known state, and a high >
low transition triggers a sync (Default = 0b).
1 = Power-Down the References for the Distribution Section (Default = 0b).
1 = Power-Down the SYNC (Default = 0b).
<6>
0
0
1
1
Not Used.
Not Used.
1 written to this bit updates all registers and transfers all serial control port register buffer
contents to the control registers on the next rising SCLK edge. This is a self-clearing bit. 0 does
not have to be written to clear it.
Not Used.
Rev. A | Page 42 of 48
<5>
0
1
0
1
Function
RESETB (Default)
SYNCB
Test Only; Do Not Use
PDB