LMK02000ISQ/NOPB National Semiconductor, LMK02000ISQ/NOPB Datasheet - Page 5

IC CLOCK CONDITIONER PREC 48-LLP

LMK02000ISQ/NOPB

Manufacturer Part Number
LMK02000ISQ/NOPB
Description
IC CLOCK CONDITIONER PREC 48-LLP
Manufacturer
National Semiconductor
Type
Clock Conditionerr
Datasheet

Specifications of LMK02000ISQ/NOPB

Pll
Yes
Input
Clock
Output
LVDS, LVPECL
Number Of Circuits
1
Ratio - Input:output
2:8
Differential - Input:output
Yes/Yes
Frequency - Max
800MHz
Divider/multiplier
Yes/No
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LLP
Frequency-max
800MHz
For Use With
LMK02000EVAL-1 - BOARD EVAL WITH 245.76 VCXOLMK02000EVAL2 - BOARD EVALUATION FOR LMK02000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
LMK02000ISQ
LMK02000ISQTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LMK02000ISQ/NOPB
Manufacturer:
Intersil
Quantity:
106
f
I
I
I
I
I
I
PN10kHz
PN1Hz
Jitter
t
V
ΔV
V
ΔV
I
I
I
COMP
SRCE
SINK
CPout
CPout
CPout
CPout
SKEW
SA
SB
SAB
OD
OS
Symbol
OD
OS
CPout
ADD
CPout
TRI
%MIS
VTUNE
TEMP
Phase Detector Frequency
Charge Pump Source Current
Charge Pump Sink Current
Charge Pump TRI-STATE
Magnitude of Charge Pump
Sink vs. Source Current Mismatch
Magnitude of Charge Pump
Current vs. Charge Pump Voltage
Variation
Magnitude of Charge Pump Current vs.
Temperature Variation
PLL 1/f Noise at 10 kHz Offset (Note 7)
Normalized to 1 GHz Output Frequency
Normalized Phase Noise Contribution
(Note 8)
Additive RMS Jitter (Note 9)
CLKoutX to CLKoutY (Note 10)
Differential Output Voltage
Change in magnitude of V
complementary output states
Output Offset Voltage
Change in magnitude of V
complementary output states
Clock Output Short Circuit Current
single ended
Clock Output Short Circuit Current
differential
Clock Distribution Section (Note 9) - LVDS Clock Outputs (CLKout0 to CLKout2)
Parameter
OD
OS
®
Current
for
for
V
V
V
V
V
V
V
V
0.5 V < V
V
T
0.5 V < V
T
PLL_CP_GAIN = 1x
PLL_CP_GAIN = 32x
PLL_CP_GAIN = 1x
PLL_CP_GAIN = 32x
R
Distribution Path =
800 MHz
Bandwidth =
12 kHz to 20 MHz
Equal loading and identical clock
configuration
R
R
R
R
R
Single ended outputs shorted to GND
Complementary outputs tied together
A
A
CPout
CPout
CPout
CPout
CPout
CPout
CPout
CPout
CPout
L
L
L
L
L
L
= 25°C
= 25°C
= 100 Ω
= 100 Ω
= 100 Ω
= 100 Ω
= 100 Ω
= 100 Ω
PLL
= Vcc/2, PLL_CP_GAIN = 1x
= Vcc/2, PLL_CP_GAIN = 4x
= Vcc/2, PLL_CP_GAIN = 16x
= Vcc/2, PLL_CP_GAIN = 32x
= Vcc/2, PLL_CP_GAIN = 1x
= Vcc/2, PLL_CP_GAIN = 4x
= Vcc/2, PLL_CP_GAIN = 16x
= Vcc/2, PLL_CP_GAIN = 32x
= Vcc / 2
5
CPout
CPout
Conditions
< Vcc - 0.5 V
< Vcc - 0.5 V
CLKoutX_MUX
= Bypass
CLKoutX_MUX
= Divided
CLKoutX_DIV =
4
1.070
Min
250
-30
-50
-35
-24
-12
-1600
-3200
1600
3200
-100
-400
-117
-122
-219
-224
1.25
Typ
100
400
350
20
75
±4
2
3
4
4
1.370
Max
450
40
10
30
50
35
24
12
www.national.com
dBc/Hz
dBc/Hz
Units
MHz
mV
mV
mV
mA
mA
µA
μA
nA
ps
%
%
%
fs
V

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