ics1523 Integrated Device Technology, ics1523 Datasheet
ics1523
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ics1523 Summary of contents
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... VGA to beyond UXGA. The ICS1523 offers clock outputs in both differential (to 250 MHz) and single-ended (to 150 MHz) formats. Dynamic Phase Adjust (DPA) allows I the output clock’s phase relative to the input sync signal ...
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... OSC input with a 7 bit input divider. See Section 6, “OSC Divider and REF” 1.3 Phase-Locked Loop (PLL) The phase-locked loop has a very wide input frequency range (8 kHz to 100 MHz). Not only is the ICS1523 an excellent, general purpose clock synthesizer, but it is also capable of line-locked operation. MDS ICS1523 Z Integrated Device Technology, Inc ...
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... The interface uses 12 indexed registers: one write-only, eight read/write, and three read-only registers. Two ICS1523 devices can be addressed according to the state of the I2CADR pin. When this pin is low the read address is 4Dh and the write address is 4Ch. ...
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... OD OUT 21 CLK+ 22 CLK/2– OD OUT 23 CLK/ IREF Note 1: These LVTTL inputs are 5 V-tolerant. Note 2: Connect to ground if unused. MDS ICS1523 Z Integrated Device Technology, Inc. Video Clock Synthesizer with I DESCRIPTION COMMENTS Digital supply 3 digital sections Digital ground 2 Serial data I C-bus Data 2 ...
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... Section 3 Functional Block Diagram MDS ICS1523 Z Integrated Device Technology, Inc. Video Clock Synthesizer with I 5 Tech Support: www.idt.com/go/clockhelp ICS1523 2 C Programmable Delay Revision 052407 ...
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... Note 1: Double-buffered register. Working registers are loaded during software PLL reset. See 0x8. Note 2: Double-buffered register. Working registers are loaded during software DPA reset. See 0x8. Notes 3~8: See Section 5, “Register Set Details” MDS ICS1523 Z Integrated Device Technology, Inc. Video Clock Synthesizer with I Reset ...
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... Chip Ver Read Chip Ver 0x11 Chip Rev Read Chip Rev 0x12 Rd_Reg Read Reserved PLL_Lock Reserved MDS ICS1523 Z Integrated Device Technology, Inc. Video Clock Synthesizer with I Bit # Reset Value 0 0 Output Enable for PECL CLK (Pins 20, 21) 0=High Z, 1=Enabled 1 0 Output Enable for STTL_3 CLK (Pin 17) ...
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... CLK Divider 0x6 bit 7 (default SSTL_3 CLK Freq. = Output Freq. / CLK Divider MDS ICS1523 Z Integrated Device Technology, Inc. Video Clock Synthesizer with I Note 6 - ICP - Charge Pump Current 0x1 Bit 2 ...
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... DPA software reset (0x8=xA) For more details, See Figure 11.2 Section 6 OSC Divider and REF The ICS1523 accepts a single-ended clock on pin 12, the OSC input. The period of this input signal becomes the high time of the REF signal and the low time is controlled by 0x7:0~6. ...
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... V DD RSET V CC 0.1µF I PECL * I PECL * * Coaxial cable, microstrip, or stripline, with Z coaxial cable, microstrip, or stripline is not required if the distance from the ICS1523 to the PECL load is short (that is, < 3 cm). 10 Tech Support: www.idt.com/go/clockhelp ICS1523 2 C Programmable Delay C 0.1µ Destination ...
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... Where external capacitance is minimal and substantial voltage swing is required to meet LVTTL V requirements, the intrinsic rise and fall times of ICS1523 SSTL_3 outputs are only slightly improved by termination in a low impedance. MDS ICS1523 Z Integrated Device Technology, Inc. ...
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... LSB Device address Repeat START ICS1523 (Slave Device) drives signal to Bus Master C register automatically increments after each successive data byte is written to C register does not automatically increment, and the software must explicitly 12 Tech Support: www.idt.com/go/clockhelp ...
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... Programming Flow for Modifying PLL and DPA Settings (Coast disabled, Positive edge of HSYNC, Internal Feedback, FUNC = regenerated HSYNC, PLL lock status to LOCK (STATUS) pin Decrement Charge Pump Current Reg0x1:2~0 MDS ICS1523 Z Integrated Device Technology, Inc. Video Clock Synthesizer with I BEGIN Determine Horizontal Total HTOTAL ...
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... Using the DPA above 160 MHz is not recommended. Set DPA_OS = 0 for speeds in excess of 160 MHz to bypass the DPA. The DPA Resolution Select register (0x5:0~1) is double-buffered. Working registers are loaded only after a DPA Software reset (0x8=xA) MDS ICS1523 Z Integrated Device Technology, Inc. Video Clock Synthesizer with I Fixed delay − ...
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... PECL Clock Low to SSTL_3 Clock Low Delay T5 PECL Clock Low to FUNC High Delay T6 PECL Clock Low to PECL/2 High Clock T7 PECL Clock Low to SSTL_3 CLK/2 Delay T8 PECL Clock High Time MDS ICS1523 Z Integrated Device Technology, Inc. Video Clock Synthesizer with I Minimum Typical 0.2 ...
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... HSYNC Low to PECL CLK+ High Delay (DPA Offset = 0) T4 PECL Clock to SSTL_3 Clock Delay T5 PECL Clock to FUNC Delay T6 PECL Clock to PECL/2 Clock T7 PECL Clock to SSTL_3 CLK/2 Delay T8 PECL Clock High Time MDS ICS1523 Z Integrated Device Technology, Inc. Video Clock Synthesizer with I Minimum Typical 0.2 0.6 1.0 ...
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... For simplicity, the waveforms drawn show only the identical PECL CLK/2+ and the SSTL_3 CLK/2 signals. CLK/2- is the compliment of the CLK/2+ signal. Note that regardless of the CLK\2 phase at the assertion of FUNC, the clocks always have the same phase at the fall of FUNC, regardless of 0x2 MDS ICS1523 Z Integrated Device Technology, Inc. Video Clock Synthesizer with I HSYNC ...
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... These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the ICS1523 at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability ...
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... LOCK/REF Transition Time - Fall Note 1- V must not fall below the level given so that the correct value for IOUT can be maintained. OL Note 2- Measured at 135MHz, 3.6 VDC, 0 Note 3- Measured at 135MHz, 3.6 VDC, 0 MDS ICS1523 Z Integrated Device Technology, Inc. Video Clock Synthesizer with I Symbol Min. Max. ...
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... Table 13-5 Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case MDS ICS1523 Z Integrated Device Technology, Inc. Video Clock Synthesizer with I Symbol Conditions Min. θ Still Air JA θ 1 m/s air flow JA θ 3 m/s air flow JA θ Tech Support: www.idt.com/go/clockhelp ICS1523 ...
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... No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental MDS ICS1523 Z Integrated Device Technology, Inc. Video Clock Synthesizer with I L ± .008 ...