MC88915TEI133 IDT, Integrated Device Technology Inc, MC88915TEI133 Datasheet

MC88915TEI133

Manufacturer Part Number

MC88915TEI133

Description

IC PLL CLOCK DRIVER 28-PLCC

Manufacturer

IDT, Integrated Device Technology Inc

Type

PLL Clock Driverr

Datasheet

1.MC88915TEI70R2.pdf (19 pages)

Specifications of MC88915TEI133

Pll

Yes with Bypass

Input

TTL

Output

CMOS, TTL

Number Of Circuits

Ratio - Input:output

2:8

Differential - Input:output

No/No

Frequency - Max

133MHz

Divider/multiplier

Yes/Yes

Voltage - Supply

4.75 V ~ 5.25 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

28-PLCC

Frequency-max

133MHz

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Available stocks

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Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

MC88915TEI133R2

Manufacturer:

MAX

Quantity:

7 284

Company:

BOSTOCK HK LIMITED

Part Number:

MC88915TEI133R2

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

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Low Skew CMOS PLL Clock Drivers, 3-State

55, 70, 100, 133, and 160 MHz Versions

IDT™ / ICS™ CMOS PLL CLOCK DRIVERS

lock its low skew outputs frequencies and phase onto an input reference clock. It

is designed to provide clock distribution for high performance PCs and

workstations. For a 3.3 V version, see the MC88LV915T data sheet.

input and distribute it to multiple components on a board. The PLL also allows

the MC88915T to multiply a low frequency input clock and distribute it locally at

a higher (2X) system frequency. Multiple 88915s can lock onto a single reference

clock, ideal for applications when a central system clock must be distributed

synchronously to multiple boards (see

their rising edges. The Q5 output is inverted (180° phase shift) from the “Q”

outputs. The 2X_Q output runs at twice the “Q” output frequency, while the

Q/2 runs at 1/2 the “Q” frequency.

specification. The wiring diagrams in

configurations, creating specific input/output frequency relationships. Possible

frequency ratios of the “Q” outputs to the SYNC input are 2:1, 1:1, and 1:2.

path of the PLL. It selects between divide-by-1 and divide-by-2 of the VCO before

its signal reaches the internal clock distribution section of the chip (see

applications FREQ_SEL should be held high (÷1). If a low frequency reference

clock input is used, holding FREQ_SEL low (÷2) allows the VCO to run in its

optimal range (>20 MHz and >40 MHz for the TFN133 version).

PLL_EN pin low disables the VCO and puts the 88915 in a static “test mode.” In

this mode, there is no frequency limitation on the input clock, necessary for a low

frequency board test environment. The second SYNC input can be used as a test

clock input to further simplify board-level testing (see

INFORMATION FOR ALL VERSIONS on page

2 into a high impedance state (3-state). After the

OE/RST pin goes back high Q0–Q4, Q5, and Q/2 will be reset in the low state,

with 2X_Q being the inverse of the selected SYNC input. Assuming PLL_EN is

low, the outputs will remain reset until the 88915 sees a SYNC input pulse.

go low if phase-lock is lost, or when the PLL_EN pin is low. The LOCK output will go high no later than 10 ms after the 88915

sees a SYNC signal and full 5.0 V V

Features

•

The MC88915T Clock Driver utilizes phase-locked loop (PLL) technology to

The PLL allows the high current, low skew outputs to lock onto a single clock

Five “Q” outputs (Q0–Q4) are provided with less than 500 ps skew between

The VCO is designed to run optimally between 20 MHz and the 2X_Q f

The FREQ_SEL pin provides one bit programmable divide-by in the feedback

In normal phase-locked operation the PLL_EN pin is held high. Pulling the

Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q0–Q4, Q5, and Q/

A lock indicator output (LOCK) will go high when the loop is in steady-state phase and frequency lock. The LOCK output will

Five outputs (Q0–Q4) with output-output skew < 500 ps, each being phase and frequency locked to the SYNC input

The phase variation from part-to-part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the t

specification, defining the part-to-part skew).

Input/output phase-locked frequency ratios of 1:2, 1:1, and 2:1 are available

Input frequency range from 5 MHz – 2X_Q f

Additional outputs available at 2X and +2 the system “Q” frequency. Also, a Q (180° phase shift) output available

All outputs have ±36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs are

TTL-level compatible. ±88 mA I

Test mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes.

All outputs can go into high impedance (3-state) for board test purposes.

Lock indicator (LOCK) accuracy indicates a phase-locked state.

28-lead Pb-free package available.

Figure 7

Figure

specifications guarantee 50 Ω transmission line switching on the incident edge.

9).

detail the different feedback

12).

max

specification (10 MHz – 2X_Q f

APPLICATIONS

). In most

max

for the TFN133 version)

MC88915TFN100

MC88915TFN133

MC88915TFN160

MC88915TFN70

MC88915TFN55

28-LEAD PLCC PACKAGE

PLL CLOCK DRIVER

LOW SKEW CMOS

Pb-FREE PACKAGE

CASE 766-02

FN SUFFIX

EI SUFFIX

MC88915TREV 7 JULY 10, 2007

MC88915T

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MC88915TEI133 Summary of contents

Page 1

Low Skew CMOS PLL Clock Drivers, 3-State 55, 70, 100, 133, and 160 MHz Versions The MC88915T Clock Driver utilizes phase-locked loop (PLL) technology to lock its low skew outputs frequencies and phase onto an input reference clock ...

Page 2

MC88915T LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE Table 1. Pin Summary Pin Name Number SYNC[0] 1 SYNC[1] 1 REF_SEL 1 FREQ_SEL 1 FEEDBACK 1 RC1 1 Q(0– 2x_Q 1 Q/2 1 LOCK 1 OE/RST 1 PLL_EN ...

Page 3

MC88915T LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE FEEDBACK SYNC ( SYNC (1) 1 REF_SEL PLL_EN FREQ_SEL OE/RST IDT™ / ICS™ CMOS PLL CLOCK DRIVERS PHASE/FREQ CHARGE PUMP/LOOP DETECTOR FILTER 0 1 MUX (÷ ...

Page 4

MC88915T LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE Table 2. SYNC Input Timing Requirements Symbol t , SYNC Inputs Rise/Fall Time, SYNC Inputs from 0.8 to 2.0 V RISE/FALL t , SYNC Inputs Input Clock Period SYNC Inputs CYCLE Duty ...

Page 5

MC88915T LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE MC88915TFN55 AND MC88915TFN70 (Continued) Table 5. Frequency Specifications (T Symbol (1) f Maximum Operating Frequency (2X_Q Output) max Maximum Operating Frequency (Q0–Q4, Q5 Output) 1. Maximum Operating Frequency is guaranteed with the ...

Page 6

MC88915T LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE Table 7. SYNC Input Timing Requirements Symbol t , SYNC Inputs Rise/Fall Time, SYNC Inputs from 0.8 to 2.0 V RISE/FALL t , SYNC Inputs Input Clock Period SYNC Inputs CYCLE Duty ...

Page 7

MC88915T LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE Table 11. AC Characteristics (T = –40°C to +85° Symbol Parameter t Rise/Fall Time, All Outputs RISE/FALL (Between 0.2 V and 0.8 V Outputs CC t Rise/Fall Time into a ...

Page 8

MC88915T LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE Table 12. SYNC Input Timing Requirements Symbol t , SYNC Inputs Rise/Fall Time, SYNC Inputs from 0.8 to 2.0 V RISE/FALL t , SYNC Inputs Input Clock Period SYNC Inputs CYCLE Duty ...

Page 9

MC88915T LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE Table 16. AC Characteristics (T = –40°C to +85° Symbol Parameter t Rise/Fall Time, All Outputs RISE/FALL (Between 0.2 V and 0.8 V Outputs CC t Rise/Fall Time into a ...

Page 10

MC88915T LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE Table 17. SYNC Input Timing Requirements Symbol t , SYNC Inputs Rise/Fall Time, SYNC Inputs from 0.8 to 2.0 V RISE/FALL t , SYNC Inputs Input Clock Period SYNC Inputs CYCLE Duty ...

Page 11

MC88915T LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE Table 21. AC Characteristics (T = 0°C to +70° Symbol Parameter t Rise/Fall Time, All Outputs RISE/FALL (Between 0.2 V and 0.8 V Outputs CC t Rise/Fall Time RISE/FALL 2X_Q ...

Page 12

MC88915T LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE APPLICATIONS INFORMATION FOR ALL VERSIONS General AC Specification Notes 1. Statistical characterization techniques were used to guarantee those specifications which cannot be measured on the ATE. MC88915 devices were fabricated with key ...

Page 13

MC88915T LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE RC1 EXTERNAL LOOP FILTER 330 Ω R2 0.1 µF C1 With the 1.0 MΩ resistor tied in this fashion, the t specification measured at the input pins is 2.25 ns ...

Page 14

MC88915T LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE –0.50 –0.75 –1.00 –1.25 –1.50 2.5 5.0 7.5 10.0 SYNC INPUT FREQUENCY (MHz) Figure 5a t versus Frequency Variation for Q/2 Output Fed PD Back, Including Process and Voltage Variation @ 25°C ...

Page 15

MC88915T LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE SYNC INPUT (SYNC[1] OR SYNC[0]) FEEDBACK INPUT Q/2 OUTPUT t SKEWALL Q0–Q4 OUTPUTS Q5 OUTPUT 2X_Q OUTPUT Figure 6. Output/Input Switching Waveforms and Timing Diagrams (These waveforms represent the hook-up configuration of ...

Page 16

MC88915T LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE 25 MHz FEEDBACK SIGNAL HIGH RST FEEDBACK LOW REF_SEL CRYSTAL 25 MHz INPUT SYNC[0] OSCILLATOR ANALOG V CC EXTERNAL LOOP RC1 FILTER ANALOG GND FQ_SEL HIGH Figure 7a. Wiring Diagram and Frequency ...

Page 17

MC88915T LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE 0.1 µF HIGH 10 µF LOW FREQUENCY FREQUENCY BYPASS BYPASS Figure 8. Recommended Loop Filter and Analog Isolation Scheme for the MC88915T 1. Figure 8 shows a loop filter and analog isolation ...

Page 18

MC88915T LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE CLOCK SYSTEM CLOCK SOURCE DISTRIBUTE CLOCK @ f CLOCK @ 2f AT POINT OF USE Figure 9. Representation of a Potential Multi-Processing Application Utilizing the MC88915T for Frequency Multiplication and Low Board-to-Board ...

Page 19

MC88915T LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 netcom@idt.com 408-284-8200 480-763-2056 Fax: 408-284-2775 Corporate Headquarters Asia Pacific and Japan Integrated Device Technology, Inc. Integrated ...

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