MC88915TEI133 IDT, Integrated Device Technology Inc, MC88915TEI133 Datasheet - Page 16

• Manufacturer Part Number: MC88915TEI133
• Description: IC PLL CLOCK DRIVER 28-PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of MC88915TEI133

• Pll: Yes with Bypass
• Input: TTL
• Output: CMOS, TTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: No/No
• Frequency - Max: 133MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Frequency-max: 133MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ / ICS™ CMOS PLL CLOCK DRIVERS
MC88915T
LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE
OSCILLATOR
OSCILLATOR
OSCILLATOR
CRYSTAL
CRYSTAL
CRYSTAL
100 MHz INPUT
25 MHz INPUT
50 MHz INPUT
EXTERNAL
EXTERNAL
EXTERNAL
FILTER
FILTER
FILTER
LOOP
LOOP
LOOP
LOW
LOW
LOW
25 MHz FEEDBACK SIGNAL
50 MHz FEEDBACK SIGNAL
100 MHz FEEDBACK SIGNAL
Figure 7c. Wiring Diagram and Frequency Relationships with 2X_Q Output Feedback
Figure 7a. Wiring Diagram and Frequency Relationships with Q/2 Output Feedback
Figure 7b. Wiring Diagram and Frequency Relationships with Q4 Output Feedback
FEEDBACK
REF_SEL
SYNC[0]
ANALOG V
RC1
ANALOG GND
FEEDBACK
REF_SEL
SYNC[0]
ANALOG V
RC1
ANALOG GND
FEEDBACK
REF_SEL
SYNC[0]
ANALOG V
RC1
ANALOG GND
FQ_SEL
FQ_SEL
FQ_SEL
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
RST
RST
RST
CC
CC
CC
Q5
Q0
Q5
Q0
Q5
Q0
MC88915T
MC88915T
MC88915T
Q4
Q4
Q4
Q1 PLL_EN
Q1 PLL_EN
Q1 PLL_EN
2X_Q
2X_Q
2X_Q
HIGH
HIGH
HIGH
Figure 7. Wiring Diagrams
Q/2
Q/2
Q/2
100 MHz SIGNAL
Q3
Q2
100 MHz SIGNAL
Q3
Q2
Q3
Q2
25 MHz
SIGNAL
25 MHz
SIGNAL
50 MHz
“Q” CLOCK
OUTPUTS
50 MHz
“Q” CLOCK
OUTPUTS
NOTE: If the OE/RST input is active, a pullup or pull-down
resistor isn’t necessary at the FEEDBACK pin so it won’t
when the fed back output goes into 3-state.
16
50 MHz
“Q” CLOCK
OUTPUTS
1:2 Input to “Q” Output Frequency Relationship
In this application, the Q/2 output is connected to
the FEEDBACK input. The internal PLL will line up
the positive edges of Q/2 and SYNC, thus the Q/2
frequency will equal the SYNC frequency. The “Q”
outputs (Q0–Q4, Q5) will always run at 2X the Q/2
frequency, and the 2X_Q output will run at 4X the
Q/2 frequency.
Allowable Input Frequency Range:
5 MHz to (2X_Q FMAX Spec)/4 (for FREQ_SEL HIGH)
2.5 MHz to (2X_Q FMAX Spec)/8 (for FREQ_SEL LOW)
1:1 Input to “Q” Output Frequency Relationship
In this application, the Q4 output is connected to
the FEEDBACK input. The internal PLL will line up
the positive edges of Q4 and SYNC, thus the Q4
frequency (and the rest of the “Q” outputs) will
equal the SYNC frequency. The Q/2 output will
always rn at 1/2 the “Q” frequency, and the 2X_Q
output will run at 2X the “Q” frequency.
Allowable Input Frequency Range:
10 MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL HIGH)
5 MHz to (2X_Q FMAX Spec)/8 (for FREQ_SEL LOW)
2:1 Input to “Q” Output Frequency Relationship
In this application, the 2X_Q output is connected to
the FEEDBACK input. The internal PLL will line up
the positive edges of 2X_Q and SYNC, thus the
2X_Q frequency will equal the SYNC frequency.
The Q/2 output will always run at 1/3 the 2X_Q
frequency, and the “Q” outputs will run at 1/2 the
2X_Q frequency.
Allowable Input Frequency Range:
20 MHz to (2X_Q FMAX Spec) (for FREQ_SEL HIGH)
10 MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL LOW)
MC88915TREV 7 JULY 10, 2007