MC88915TEI133 IDT, Integrated Device Technology Inc, MC88915TEI133 Datasheet - Page 17

• Manufacturer Part Number: MC88915TEI133
• Description: IC PLL CLOCK DRIVER 28-PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of MC88915TEI133

• Pll: Yes with Bypass
• Input: TTL
• Output: CMOS, TTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: No/No
• Frequency - Max: 133MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Frequency-max: 133MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ / ICS™ CMOS PLL CLOCK DRIVERS
MC88915T
LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE
1.
Figure 8
which will be effective in most applications. The
following guidelines should be followed to ensure stable
and jitter-free operation:
a.
b.
FREQUENCY
All loop filter and analog isolation components
should be tied as close to the package as possible.
Stray current passing through the parasitics of long
traces can cause undesirable voltage transients at
the RC1 pin.
The 47 Ω resistors, the 10 µF low frequency bypass
capacitor, and the 0.1 µF high frequency bypass
capacitor form a wide bandwidth filter minimizing
the 88915T’s sensitivity to voltage transients from
the system digital V
This filter will typically ensure a 100 mV step
deviation on the digital V
more than a 100 ps phase deviation o the 88915T
outputs. A 250 mV step deviation on VCC using the
recommended filter values should cause no more
than 250 ps phase deviation; if a 25 µF bypass
capacitor is used (instead of 10 µF) a 250 mV V
step should cause no more than a 100 ps phase
deviation.
If good bypass techniques are used on a board
design near components potentially causing digital
V
step deviations should not occur at the 88915T’s
digital V
filtering scheme shown in
10 µF LOW
CC
BYPASS
shows a loop filter and analog isolation scheme
and ground noise, the above described V
CC
Figure 8. Recommended Loop Filter and Analog Isolation Scheme for the MC88915T
supply. The purpose of the bypass
FREQUENCY
CC
0.1 µF HIGH
supply and ground planes.
BYPASS
CC
Figure 8
supply, causing no
Notes Concerning Loop Filter and Board Layout Issues
is to give the
1.5 MΩ
1 MΩ
47 Ω
47 Ω
BOARD V
or
BOARD GND
CC
CC
CC
0.1 µF (LOOP
FILTER CAP)
330 Ω
NOTE:
17
2.
c.
d.
In addition to the bypass capacitors used in the analog
filter of
capacitor between each of the other (digital) four V
pins and the board ground plane. This will reduce output
switching noise caused by the 88915T outputs. In
addition to reducing potential for noise in the “analog”
section of the chip. These bypass capacitors should
also be tied as close to the 88915T package as
possible.
A separate analog power supply is not necessary and
should not be used. Following these prescribed guidelines
is all that is necessary to use the MC88915T in a normal
digital environment.
88915T additional protection from the power supply
and ground plane transients potentially occurring in
a high frequency, high speed digital system.
There are no special requirements set forth for the
loop filter resistors (1.0 MΩ and 330 Ω). The loop
filter capacitor (0.1 µF) can be a ceramic chip
capacitor, the same as a standard bypass
capacitor.
The 1.0 M reference resistor injects current into the
internal charge pump of the PLL, causing a fixed
offset between the outputs and the SYNC input.
This also prevents excessive jitter caused by
inherent PLL dead-band. If the VCO (2X_Q output)
is running above 40 MHz, the 1.0 MΩ resistor
provides the correct amount of current injection into
the charge pump
running below 40 MHz, a 1.5 MΩ reference resistor
should be used (instead of 1 MΩ).
(2–3 µA). For the TFN55, 70 or 100, if the VCO is
10
8
9
Figure
ANALOG VCC
RC1
ANALOG GND
8, there should be a 0.1 µF bypass
ANALOG LOOP FILTER/VCO
SECTION OF THE MC88915T
28-PIN PLCC PACKAGE (NOT
DRAWN TO SCALE)
MC88915TREV 7 JULY 10, 2007
CC