MC88915TEI133 IDT, Integrated Device Technology Inc, MC88915TEI133 Datasheet - Page 7

• Manufacturer Part Number: MC88915TEI133
• Description: IC PLL CLOCK DRIVER 28-PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of MC88915TEI133

• Pll: Yes with Bypass
• Input: TTL
• Output: CMOS, TTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: No/No
• Frequency - Max: 133MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Frequency-max: 133MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ / ICS™ CMOS PLL CLOCK DRIVERS
Table 11. AC Characteristics (T
MC88915T
LOW SKEW CMOS PLL CLOCK DRIVERS, 3-STATE
t
Outputs
t
2X_Q Output
t
(Q0–Q4, Q5, Q/2)
t
(2X_Q Output)
t
(2X_Q Output)
t
SYNC Feedback
t
(Rising)
t
(Falling)
t
t
t
t
RISE/FALL
RISE/FALL
PULSEWIDT
PULSEWIDTH
PULSEWIDTH
PD
SKEWr
SKEWf
SKEWall
LOCK
PZL
PHZ
1. These specifications are not tested. They are guaranteed by statistical characterization. See AC specification Note 1.
2. t
3. The t
4. Under equally loaded conditions and at a fixed temperature and voltage.
5. With V
(1),(3)
with C1 = 0.01 µF.
, t
CYCLE
Symbol
(5)
PLZ
(4)
(1),(4)
(5)
(1),(4)
PD
CC
in this spec is 1/Frequency at which the particular output is running.
(1)
specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
(1)
(1)
fully powered on, and an output properly connected to the FEEDBACK pin. t
Rise/Fall Time, All Outputs
(Between 0.2 V
Rise/Fall Time into a 20 pF Load, with Termination
Specified in Note
Output Pulse Width: Q0, Q1, Q2, Q4, Q4,
Q5, Q/2 @ V
Output Pulse Width: 2X_Q @ 1.5 V
Output Pulse Width: 40 – 49 MHz
2X_Q @ V
66 – 100 MHz
SYNC Input to Feedback Delay
(Measured at SYNC0 or 1
and FEEDBACK Input Pins)
Output-to-Output Skew Between Outputs Q0–Q4,
Q/2 (Rising Edges Only)
Output-to-Output Skew Between Outputs Q0–Q4
(Falling Edges Only)
Output-to-Output Skew 2X_Q, Q/2, Q0–Q4 Rising,
Q5 Falling
Time Required to Acquire Phase-Lock from Time
SYNC Input Signal is Received
Output Enable Time OE/RST to 2X_Q, Q0–Q4,
Q5, and Q/2
Output Disable Time OE/RST to 2X_Q, Q0–Q4,
Q5, and Q/2
CC
CC
/250 – 65 MHz
CC
/2
(2)
A
and 0.8 V
= –40°C to +85°C, V
Parameter
CC
)
MC88915TFN100 (Continued)
CC
= 5.0 V ± 5%, Load = 50 Ω Terminated to V
0.5 t
0.5 t
0.5 t
0.5 t
0.5 t
(With 1 MΩ from RC1 to An GND)
(With 1 MΩ from RC1 to An V
7
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
+1.25
–1.05
Min
1.0
0.5
1.0
3.0
3.0
—
—
—
– 0.5
– 0.5
– 1.5
– 1.0
– 0.5
(2)
(2)
(2)
LOCK
0.5 t
0.5 t
0.5 t
0.5 t
0.5 t
CYCLE
CYCLE
CYCLE
maximum is with C1 = 0.1 µF, t
CYCLE
CYCLE
+3.25
–0.30
Max
500
500
750
2.5
1.6
10
14
14
+ 0.5
+ 0.5
+ 1.5
+ 1.0
+ 0.5
CC
)
(2)
(2)
(2)
Unit
ms Also Time to LOCK
ns
ns
ns
ns
ns
ns
ps
ps
ps
ns
ns
CC
Into a 50 Ω Load
Terminated to V
t
t
Into a 50 Ω Load
Terminated to V
Must Use Termination
Specified in Note
Into a 50 Ω Load
Terminated to V
See Note
for Detailed Explanation
All Outputs into a Matched
50 Ω Load Terminated to
V
All Outputs into a Matched
50 Ω Load Terminated to
V
All Outputs into a Matched
50 Ω Load Terminated to
V
Indicator High
Measured with the
PLL_EN Pin Low
Measured with the
PLL_EN Pin Low
RISE
FALL
CC
CC
CC
/2)
MC88915TREV 7 JULY 10, 2007
/2
/2
/2
: 0.8 V – 2.0 V
: 2.0 V – 0.8 V
Condition
(4)
LOCK
and
minimum is
CC
CC
CC
Figure 4
(2)
/2
/2
/2