IDT82V3380PFG IDT, Integrated Device Technology Inc, IDT82V3380PFG Datasheet - Page 105

• Manufacturer Part Number: IDT82V3380PFG
• Description: IC PLL WAN SYNC ETH 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3380PFG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3380PFG

UPPER_THRESHOLD_0_CNFG - Upper Threshold for Leaky Bucket Configuration 0
LOWER_THRESHOLD_0_CNFG - Lower Threshold for Leaky Bucket Configuration 0
BUCKET_SIZE_0_CNFG - Bucket Size for Leaky Bucket Configuration 0
Programming Information
IDT82V3380
Address: 32H
Type: Read / Write
Default Value: 00000100
Address: 33H
Type: Read / Write
Default Value: 00001000
Address: 31H
Type: Read / Write
Default Value: 00000110
SHOLD_0_DAT
SHOLD_0_DAT
LOWER_THRE
UPPER_THRE
7 - 0
7 - 0
BUCKET_SIZE
7 - 0
Bit
Bit
Bit
_0_DATA7
A7
A7
7
7
7
UPPER_THRESHOLD_0_DATA[7:0]
LOWER_THRESHOLD_0_DATA[7:0]
BUCKET_SIZE_0_DATA[7:0]
SHOLD_0_DAT
SHOLD_0_DAT
LOWER_THRE
UPPER_THRE
BUCKET_SIZE
_0_DATA6
Name
Name
Name
A6
A6
6
6
6
LOWER_THRE
SHOLD_0_DAT
SHOLD_0_DAT
UPPER_THRE
BUCKET_SIZE
These bits set a bucket size for the internal leaky bucket accumulator. If the number of the accumulated events reach
the bucket size, the accumulator will stop increasing even if further events are detected.
_0_DATA5
A5
A5
5
5
5
These bits set an upper threshold for the internal leaky bucket accumulator. When the number of the accumu-
lated events is above this threshold, a no-activity alarm is raised.
These bits set a lower threshold for the internal leaky bucket accumulator. When the number of the accumulated
events is below this threshold, the no-activity alarm is cleared.
LOWER_THRE
SHOLD_0_DAT
SHOLD_0_DAT
UPPER_THRE
BUCKET_SIZE
_0_DATA4
A4
A4
4
4
4
105
SHOLD_0_DAT
SHOLD_0_DAT
LOWER_THRE
UPPER_THRE
BUCKET_SIZE
_0_DATA3
A3
A3
3
3
3
Description
Description
Description
SHOLD_0_DAT
SHOLD_0_DAT
LOWER_THRE
UPPER_THRE
BUCKET_SIZE
_0_DATA2
A2
A2
2
2
2
SYNCHRONOUS ETHERNET WAN PLL
LOWER_THRE
SHOLD_0_DAT
SHOLD_0_DAT
UPPER_THRE
BUCKET_SIZE
_0_DATA1
A1
A1
1
1
1
LOWER_THRE
SHOLD_0_DAT
SHOLD_0_DAT
UPPER_THRE
BUCKET_SIZE
_0_DATA0
May 19, 2009
A0
A0
0
0
0