IDT82V3380PFG IDT, Integrated Device Technology Inc, IDT82V3380PFG Datasheet - Page 14

• Manufacturer Part Number: IDT82V3380PFG
• Description: IC PLL WAN SYNC ETH 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3380PFG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3380PFG

Table 1: Pin Description (Continued)
Pin Description
IDT82V3380
MFRSYNC_2K
FRSYNC_8K
IN5_POS
IN5_NEG
IN6_POS
IN6_NEG
Name
OUT1
IN10
IN11
IN12
IN13
IN14
IN7
IN8
IN9
Pin No.
40
41
42
43
48
51
52
53
54
55
56
57
30
31
88
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
pull-down
I/O
O
O
O
I
I
I
I
I
I
I
I
I
I
PECL/LVDS
PECL/LVDS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Type
Output Frame Synchronization Signal
IN5_POS / IN5_NEG: Positive / Negative Input Clock 5
A 2 kHz, 4 kHz, N x 8 kHz
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 156.25 MHz, 311.04 MHz or
622.08 MHz clock is differentially input on this pair of pins. Whether the clock signal is PECL
or LVDS is automatically detected.
Single-ended input for differential input is also supported. Refer to
Ended Input for Differential
IN6_POS / IN6_NEG: Positive / Negative Input Clock 6
A 2 kHz, 4 kHz, N x 8 kHz
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 156.25 MHz, 311.04 MHz or
622.08 MHz clock is differentially input on this pair of pins. Whether the clock signal is PECL
or LVDS is automatically detected.
Single-ended input for differential input is also supported. Refer to
Ended Input for Differential
IN7: Input Clock 7
A 2 kHz, 4 kHz, N x 8 kHz
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
IN8: Input Clock 8
A 2 kHz, 4 kHz, N x 8 kHz
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
IN9: Input Clock 9
A 2 kHz, 4 kHz, N x 8 kHz
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
IN10: Input Clock 10
A 2 kHz, 4 kHz, N x 8 kHz
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
IN11: Input Clock 11
A 2 kHz, 4 kHz, N x 8 kHz
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
In Slave operation, the frequency of the T0 selected input clock IN11 is recommended to be
6.48 MHz.
IN12: Input Clock 12
A 2 kHz, 4 kHz, N x 8 kHz
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
IN13: Input Clock 13
A 2 kHz, 4 kHz, N x 8 kHz
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
IN14: Input Clock 14
A 2 kHz, 4 kHz, N x 8 kHz
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
FRSYNC_8K: 8 kHz Frame Sync Output
An 8 kHz signal is output on this pin.
MFRSYNC_2K: 2 kHz Multiframe Sync Output
A 2 kHz signal is output on this pin.
OUT1: Output Clock 1
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz or 155.52 MHz clock is output on this pin.
Output Clock
14
3
3
3
3
3
3
3
3
3
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
Input.
Input.
Description
SYNCHRONOUS ETHERNET WAN PLL
4
, N x T1
1
5
, N x 13.0 MHz
Chapter 9.3.3.3 Single-
Chapter 9.3.3.3 Single-
6
, N x 3.84 MHz
May 19, 2009
7
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