EL4584CS Intersil, EL4584CS Datasheet - Page 4

• Manufacturer Part Number: EL4584CS
• Description: IC PLL VIDEO GP 36MHZ 16-SOIC
• Manufacturer: Intersil
• Type: Phase Lock Loop (PLL)r

Specifications of EL4584CS

• Pll: Yes
• Input: Clock
• Output: CMOS, TTL
• Number Of Circuits: 1
• Ratio - Input:output: 3:1
• Differential - Input:output: No/No
• Frequency - Max: 36MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 5V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Frequency-max: 36MHz
• Number Of Elements: 1
• Supply Current: 4mA
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC
• Operating Temperature Classification: Industrial
• Pin Count: 16
• Frequency: 36MHz
• Supply Voltage Range: 5V
• Digital Ic Case Style: SOIC
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Peak Reflow Compatible (260 C): No
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pin Descriptions
PIN NUMBER
1, 2, 16
10
12
13
14
15
11
PROG A (PIN 16)
3
4
5
6
7
8
9
0
0
0
0
1
1
1
1
PROG C, PROG A
CHARGE PUMP
OSC/VCO OUT
LOCK DETECT
EXT DIVIDER
OSC/VCO IN
DIV SELECT
PIN NAME
HSYNC IN
CLK OUT
PROG B,
VDD (A)
VDD (D)
VSS (A)
VSS (D)
COAST
OUT
4
Digital inputs to select ÷ N value for internal counter. See Table 2 for values.
Output of internal inverter/oscillator. Connect to external crystal or LC tank VCO circuit.
Analog positive supply for oscillator, PLL circuits.
Input from external VCO.
Analog ground for oscillator, PLL circuits.
Connect to loop filter. If the H
into the filter capacitor to increase VCO frequency. If H
current is pumped out of the filter capacitor to decrease VCO frequency. During coast mode or when
locked, charge pump goes to a high impedance state.
Divide select input. When high, the internal divider is enabled and EXT DIV becomes a test pin, outputting
CLK ÷ N. When low, the internal divider is disabled and EXT DIV is an input from an external ÷ N.
Tri-state logic input. Low (<1/3*V
High (>2/3*V
Horizontal sync pulse (CMOS level) input.
Positive supply for digital, I/O circuits.
Lock Detect output. Low level when PLL is locked. Pulses high when out of lock.
External Divide input when DIV SEL is low, internal ÷N output when DIV SEL is high.
Ground for digital, I/O circuits.
Buffered output of the VCO.
PROG B (PIN 1)
0
0
1
1
0
0
1
1
CC
) = coast mode.
TABLE 2. VCO DIVISORS
EL4584
SYNC
CC
phase is leading or H
) = normal mode, Hi Z (or 1/3 to 2/3*V
PROG C (PIN 2)
FUNCTION
0
1
0
1
0
1
0
1
SYNC
SYNC
phase is lagging or frequency < CLK ÷ N,
frequency > CLK ÷ N, current is pumped
CC
) = fast lock mode,
DIV VALUE (N)
1135
851
864
944
682
858
780
910
May 9, 2008
FN7174.3