SI5368B-B-GQ Silicon Laboratories Inc, SI5368B-B-GQ Datasheet - Page 10

• Manufacturer Part Number: SI5368B-B-GQ
• Description: IC ANY-RATE MULTI/ATTEN 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Multiplierr

Specifications of SI5368B-B-GQ

• Number Of Circuits: 1
• Package / Case: 100-TQFP, 100-VQFP
• Pll: Yes with Bypass
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Ratio - Input:output: 4:5
• Differential - Input:output: Yes/Yes
• Frequency - Max: 808MHz
• Divider/multiplier: No/Yes
• Voltage - Supply: 1.62 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 808MHz
• Maximum Input Frequency: 710 MHz
• Minimum Input Frequency: 0.002 MHz
• Output Frequency Range: 0.002 MHz to 1417 MHz
• Supply Voltage (max): 2.75 V
• Supply Voltage (min): 1.62 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V, 2.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5368
10
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
Pin #
32
42
34
35
39
40
44
45
49
54
Pin Name
CKIN2+
CKIN2–
CKIN3+
CKIN3–
CKIN1+
CKIN1–
RATE1
RATE0
DEC
LOL
I/O
Table 3. Si5368 Pin Descriptions (Continued)
O
I
I
I
I
I
Signal Level
LVCMOS
LVCMOS
3-Level
MULTI
MULTI
MULTI
Preliminary Rev. 0.3
External Crystal or Reference Clock Rate.
Three level inputs that select the type and rate of external crys-
tal or reference clock to be applied to the XA/XB port.
Settings:
HH = No Crystal or Reference Clock. Converts part to a Si5367
MM = 114.285 MHz 3rd OT crystal (Narrowband).
LM = 38.88 MHz external clock (Narrowband).
All others = Reserved.
Clock Input 2.
Differential input clock. This input can also be driven with a sin-
gle-ended signal.
Clock Input 3.
Differential clock input. This input can also be driven with a sin-
gle-ended signal. CKIN3 serves as the frame sync input associ-
ated with the CKIN1 clock when CK_CONFIG_REG = 1.
Clock Input 1.
Differential clock input. This input can also be driven with a sin-
gle-ended signal.
PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indicator if
the LOL_PIN register bit is set to one.
0 = PLL locked.
1 = PLL unlocked.
If LOL_PIN = 0, this pin will tristate.
Active polarity is controlled by the LOL_POL bit. The PLL lock
status will always be reflected in the LOL_INT read only register
bit.
Coarse Latency Decrement.
A pulse on this pin decreases the input to output device latency
by 1/fOSC (approximately 200 ps). Detailed operations and tim-
ing characteristics for this pin may be found in the Any-Rate
Precision Clock Family Reference Manual. There is no limit on
the range of latency adjustment by this method. Pin control is
enabled by setting INCDEC_PIN = 1 (default).
If INCDEC_PIN = 0, this pin is ignored and coarse output
latency is controlled via the CLAT register.
If both INC and DEC are tied high, phase buildout is disabled
and the device maintains a fixed-phase relationship between
the selected input clock and the output clock during an input
clock switch. Detailed operations and timing characteristics for
these pins may be found in the Any-Rate Precision Clock Fam-
ily Reference Manual.
This pin has a weak pull-down.
device. See Si5367 Data Sheet for operation.
(Wideband).
Description