SI5368B-B-GQ Silicon Laboratories Inc, SI5368B-B-GQ Datasheet - Page 9

• Manufacturer Part Number: SI5368B-B-GQ
• Description: IC ANY-RATE MULTI/ATTEN 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Multiplierr

Specifications of SI5368B-B-GQ

• Number Of Circuits: 1
• Package / Case: 100-TQFP, 100-VQFP
• Pll: Yes with Bypass
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Ratio - Input:output: 4:5
• Differential - Input:output: Yes/Yes
• Frequency - Max: 808MHz
• Divider/multiplier: No/Yes
• Voltage - Supply: 1.62 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 808MHz
• Maximum Input Frequency: 710 MHz
• Minimum Input Frequency: 0.002 MHz
• Output Frequency Range: 0.002 MHz to 1417 MHz
• Supply Voltage (max): 2.75 V
• Supply Voltage (min): 1.62 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V, 2.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
Pin #
13
57
16
17
21
29
30
FS_ALIGN
Pin Name
CS0_C3A
CS1_C4A
CKIN4+
CKIN4–
XA
XB
I/O
I/O
Table 3. Si5368 Pin Descriptions (Continued)
I
I
I
Signal Level
LVCMOS
ANALOG
LVCMOS
MULTI
Preliminary Rev. 0.3
Input Clock Select/CKIN3 or CKIN4 Active Clock Indicator.
If manual clock selection is chosen, and if CKSEL_PIN = 1, the
CKSEL pins control clock selection and the CKSEL_REG bits
are ignored.
If CKSEL_PIN = 0, the CKSEL_REG register bits control this
function and these inputs tristate. If these pins are not function-
ing as the CS[1:0] inputs and auto clock selection is enabled,
then they serve as the CKIN_n active clock indicator.
0 = CKIN3 (CKIN4) is not the active input clock
1 = CKIN3 (CKIN4) is currently the active input to the PLL
The CKn_ACTV_REG bit always reflects the active clock status
for CKIN_n. If CKn_ACTV_PIN = 1, this status will also be
reflected on the CnA pin with active polarity controlled by the
CK_ACTV_POL bit. If CKn_ACTV_PIN = 0, this output tristates.
This pin has a weak pull-down.
External Crystal or Reference Clock.
External crystal should be connected to these pins to use exter-
nal oscillator based reference. If a single-ended external refer-
ence is used, ac couple reference clock to XA input and leave
XB pin floating. External reference must be from a high-quality
clock source (TCXO, OCXO). Frequency of crystal or external
clock is set by the RATE pins.
FSYNC Alignment Control.
If FSYNC_ALIGN_PIN = 1 and CK_CONFIG = 1, a logic high
on this pin causes the FS_OUT phase to be realigned to the ris-
ing edge of the currently active input sync (CKIN_3 or CKIN_4).
If FSYNC_ALIGN_PIN = 0, this pin is ignored and the
FSYNC_ALIGN_REG bit performs this function.
0 = No realignment.
1 = Realign.
This pin has a weak pull-down.
Clock Input 4.
Differential clock input. This input can also be driven with a sin-
gle-ended signal. CKIN4 serves as the frame sync input associ-
ated with the CKIN2 clock when CK_CONFIG_REG = 1.
CS[1:0]
00
01
10
11
Description
Active Input Clock
CKIN1
CKIN2
CKIN3
CKIN4
Si5368
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