SI5368B-B-GQ Silicon Laboratories Inc, SI5368B-B-GQ Datasheet - Page 2

• Manufacturer Part Number: SI5368B-B-GQ
• Description: IC ANY-RATE MULTI/ATTEN 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Multiplierr

Specifications of SI5368B-B-GQ

• Number Of Circuits: 1
• Package / Case: 100-TQFP, 100-VQFP
• Pll: Yes with Bypass
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Ratio - Input:output: 4:5
• Differential - Input:output: Yes/Yes
• Frequency - Max: 808MHz
• Divider/multiplier: No/Yes
• Voltage - Supply: 1.62 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 808MHz
• Maximum Input Frequency: 710 MHz
• Minimum Input Frequency: 0.002 MHz
• Output Frequency Range: 0.002 MHz to 1417 MHz
• Supply Voltage (max): 2.75 V
• Supply Voltage (min): 1.62 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V, 2.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5368
Table 1. Performance Specifications
(V
2
Temperature Range
Supply Voltage
Supply Current
Input Clock Frequency
(CKIN1, CKIN2, CKIN3,
CKIN4)
Input Clock Frequency
(CKIN3, CKIN4 used as
FSYNC inputs)
Output Clock Frequency
(CKOUT1, CKOUT2,
CKOUT3, CKOUT4, CKOUT5
used as fifth high-speed out-
put)
CKOUT5 used as frame sync
output (FS_OUT)
Input Clocks (CKIN1, CKIN2, CKIN3, CKIN4)
Differential Voltage Swing
Common Mode Voltage
Rise/Fall Time
Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
Duty Cycle
DD
= 1.8 or 2.5 V ±10%, T
Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
Parameter
A
= –40 to 85 ºC)
CKN
CKN
Symbol
CKN
CKN
CK
CK
V
CK
CK
I
T
DD
DD
A
OF
OF
VCM
DPP
TRF
F
F
DC
programming device PLL divid-
Manual at
Input frequency and clock mul-
DSPLLsim or Any-Rate Preci-
All CKOUTs enabled LVPECL
ers. Consult Silicon Laborato-
tiplication ratio determined by
sion Clock Family Reference
settings for a given input fre-
ing
quency/clock multiplication
ries configuration software
Only CKOUT1 enabled
Only CKOUT1 enabled
CMOS format output
to determine PLL divider
Preliminary Rev. 0.3
All CKOUTs enabled
Tristate/Sleep Mode
f
OUT
f
ratio combination.
Whichever is less
OUT
Test Condition
format output
1.8 V ±10%
2.5 V ±10%
www.silabs.com/tim-
= 622.08 MHz
20–80%
= 19.44 MHz
0.002
0.002
0.002
0.002
1213
2.25
1.62
0.25
Min
–40
970
0.9
1.0
—
—
—
—
—
—
40
50
TBD
Typ
394
253
278
229
2.5
1.8
25
—
—
—
—
—
—
—
—
—
—
—
—
0.512
1417
1134
Max
2.75
1.98
TBD
284
261
435
321
710
945
710
1.9
1.4
1.7
85
60
11
—
Unit
MHz
MHz
MHz
MHz
V
mA
mA
mA
mA
mA
ºC
ns
ns
%
V
V
V
V
PP