CY28442ZXC Cypress Semiconductor Corp, CY28442ZXC Datasheet - Page 6
![IC CLOCK GEN ALVISO 56-TSSOP](/photos/6/56/65689/428-56-tssop_sml.jpg)
CY28442ZXC
Manufacturer Part Number
CY28442ZXC
Description
IC CLOCK GEN ALVISO 56-TSSOP
Manufacturer
Cypress Semiconductor Corp
Type
Fanout Distribution, Spread Spectrum Clock Generatorr
Datasheet
1.CY28442ZXC.pdf
(22 pages)
Specifications of CY28442ZXC
Pll
Yes with Bypass
Input
LVTTL, Crystal
Output
Clock
Number Of Circuits
1
Ratio - Input:output
11:15
Differential - Input:output
No/Yes
Frequency - Max
200MHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
56-TSSOP II
Frequency-max
100MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY28442ZXC-2
Manufacturer:
CYP
Quantity:
20 000
Company:
Part Number:
CY28442ZXC-2T
Manufacturer:
TI
Quantity:
11
Company:
Part Number:
CY28442ZXC-4
Manufacturer:
SEMTEC
Quantity:
946
Document #: 38-07680 Rev. **
Byte 3: Control Register 3
Byte 4: Control Register 4
Byte 5: Control Register 5
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
@Pup
@Pup
@Pup
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
SRC[T/C][7:1]
96_100_SSC
RESERVED
RESERVED
DOT96T/C
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
CPU[T/C]2
SRC[T/C]
Name
PCIF1
PCIF0
Name
SRC7
SRC6
SRC5
SRC4
SRC3
SRC2
SRC1
Name
ADVANCE INFORMATION
Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]6 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]1 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
RESERVED
96_100_SSC Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
DOT_PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
RESERVED
Allow control of PCIF1 with assertion of SW and HW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of PCIF0 with assertion of SW and HW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of CPU[T/C]2 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Allow control of CPU[T/C]1 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Allow control of CPU[T/C]0 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
SRC[T/C] Stop Drive Mode
0 = Driven when PCI_STP# asserted,1 = Tri-state when PCI_STP#
asserted
CPU[T/C]2 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP#
asserted
CPU[T/C]1 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP#
asserted
CPU[T/C]0 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP#
asserted
SRC[T/C] PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
Description
Description
Description
CY28442
Page 6 of 22
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