MPC9774AE Freescale Semiconductor, MPC9774AE Datasheet

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MPC9774AE

Manufacturer Part Number
MPC9774AE
Description
IC PLL CLK GENERATOR 1:14 52LQFP
Manufacturer
Freescale Semiconductor
Type
Clock Generator, Fanout Distribution, Multiplexer , Zero Delay Bufferr
Datasheet

Specifications of MPC9774AE

Pll
Yes with Bypass
Input
LVCMOS
Output
LVCMOS
Number Of Circuits
1
Ratio - Input:output
2:14
Differential - Input:output
No/No
Frequency - Max
125MHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
52-LQFP
Frequency-max
125MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC9774AE
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
MPC9774AE
Manufacturer:
IDT
Quantity:
20 000
Part Number:
MPC9774AER2
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
3.3V 1:14 LVCMOS PLL Clock
Generator
targeted for high performance low-skew clock distribution in mid-range to
high-performance networking, computing and telecom applications. With
output frequencies up to 125 MHz and output skews less than 175 ps the
device meets the needs of the most demanding clock applications.
Features
Functional Description
MPC9774 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The
reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match
the VCO frequency range.
relationships. Output frequency ratios of 1:1, 2:1, 3:1, 3:2 and 3:2:1 can be realized. Additionally, the device supports a separate
configurable feedback output which allows for a wide variety of of input/output frequency multiplication alternatives. The
VCO_SEL pin provides an extended PLL input reference frequency range.
alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL
bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output
dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL
characteristics do not apply.
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission
lines. For series terminated transmission lines, each of the MPC9774 outputs can drive one or two traces giving the devices an
effective fanout of 1:12. The device is pin and function compatible to the MPC974 and is packaged in a 52-lead LQFP package.
1:14 PLL based low-voltage clock generator
3.3V power supply
Internal power–on reset
Generates clock signals up to 125 MHz
Maximum output skew of 175 ps
Two LVCMOS PLL reference clock inputs
External PLL feedback supports zero-delay capability
Various feedback and output dividers (see application section)
Supports up to three individual generated output clock frequencies
Drives up to 28 clock lines
Ambient temperature range 0°C to +70°C
Pin and function compatible to the MPC974
The MPC9774 is a 3.3V compatible, 1:14 PLL based clock generator
The MPC9774 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the
The MPC9774 features frequency programmability between the three output banks outputs as well as the output to input
The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two
The MPC9774 has an internal power–on reset.
The MPC9774 is fully 3.3V compatible and requires no external loop filter components. All inputs (except XTAL) accept
Motorola, Inc. 2003
1
PLL CLOCK GENERATOR
3.3V 1:14 LVCMOS
52 LEAD LQFP PACKAGE
MPC9774
CASE 848D
FA SUFFIX
Order Number: MPC9774/D
Rev 2, 05/2003

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MPC9774AE Summary of contents

Page 1

MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3.3V 1:14 LVCMOS PLL Clock Generator The MPC9774 is a 3.3V compatible, 1:14 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance networking, computing and telecom applications. With output frequencies ...

Page 2

MPC9774 All input resistors have a value of 25k V CC CCLK0 0 Ref CCLK1 1 CCLK_SEL PLL 200-500 MHz V CC FB_IN FB PLL_EN VCO_SEL FSEL_A FSEL_B FSEL_C 2 FSEL_FB[1: CLK_STOP V CC MR/OE Figure 2. MPC9774 ...

Page 3

Table 1. PIN CONFIGURATION Pin I/O Type CCLK0 Input LVCMOS PLL reference clock CCLK1 Input LVCMOS Alternative PLL reference clock FB_IN Input LVCMOS PLL feedback signal input, connect to QFB CCLK_SEL Input LVCMOS LVCMOS clock reference select VCO_SEL Input LVCMOS ...

Page 4

MPC9774 Table 4. Function Table (QFB) VCO_SEL FSEL_B1 FSEL_B0 Table 5. General Specifications Symbol Characteristics V ...

Page 5

T Table 8. AC Characteristics (V CC Symbol Characteristics f Input Reference Frequency REF Input Reference Frequency in PLL Bypass Mode c f VCO Frequency Range VCO f Output Frequency MAX d t Input Reference Pulse ...

Page 6

MPC9774 MPC9774 Configurations Configuring the MPC9774 amounts to properly configuring the internal dividers to produce the desired output frequencies. The output frequency can be represented by this formula: ⋅ ÷ ÷ ÷ where f is the reference frequency of the ...

Page 7

Using the MPC9774 in zero-delay applications Nested clock trees are typical applications for the MPC9774. Designs using the MPC9774 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS ...

Page 8

MPC9774 Driving Transmission Lines The MPC9774 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. ...

Page 9

Power Supply Filtering The MPC9774 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL power supply impacts the device ...

Page 10

MPC9774 Figure 13. Output–to–output Skew 100 Figure 15. Output Duty Cycle (DC JIT(CC) Figure 17. Cycle–to–cycle Jitter Figure 19. Output Transition Time Test Reference MOTOROLA B B Figure 14. Propagation ...

Page 11

VIEW Y 3X –L– –N– –H– –T– q3 SEATING 4X PLANE VIEW AA Z TIMING SOLUTIONS OUTLINE DIMENSIONS FA SUFFIX 52 ...

Page 12

MPC9774 Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on ...

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