MPC9774AE Freescale Semiconductor, MPC9774AE Datasheet - Page 3

• Manufacturer Part Number: MPC9774AE
• Description: IC PLL CLK GENERATOR 1:14 52LQFP
• Manufacturer: Freescale Semiconductor
• Type: Clock Generator, Fanout Distribution, Multiplexer , Zero Delay Bufferr

Specifications of MPC9774AE

• Pll: Yes with Bypass
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:14
• Differential - Input:output: No/No
• Frequency - Max: 125MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 125MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING SOLUTIONS
Table 1. PIN CONFIGURATION
Table 2. Function Table (MPC9774 configuration controls)
Table 3. Function Table (Output Dividers Bank A, B, and C)
CCLK0
CCLK1
FB_IN
CCLK_SEL
VCO_SEL
PLL_EN
MR/OE
CLK_STOP
FSEL_A
FSEL_B
FSEL_C
FSEL_FB[1:0]
QA[4:0]
QB[4:0]
QC[3:0]
QFB
GND
VCC_PLL
V
VCO_SEL, FSEL_A, FSEL_B, FSEL_C and FSEL_FB[1:0] control the operating PLL frequency range and input/output frequency ratios.
See
CLK_STOP
CCLK_SEL
VCO_SEL
VCO_SEL
CC
PLL_EN
Control
MR/OE
Table 3
0
0
1
1
Pin
and
Default
FSEL_A
Table 4
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Supply
Supply
Supply
0
0
1
1
1
0
1
0
1
I/O
for the device frequency configuration.
Selects CCLK0 as PLL refererence signal input
Selects VCO ÷ 2. The VCO frequency is scaled by a
factor of 2 (high input frequency range)
Test mode with the PLL bypassed. The reference clock is
substituted for the internal VCO output. MPC9774 is fully
static and no minimum frequency limit applies. All PLL
related AC characteristics are not applicable.
QA, QB an QC outputs disabled in logic low state. QFB
is not affected by CLK_STOP. CLK_STOP deassertion
may cause the initial output clock pulse to be distorted.
Outputs disabled (high-impedance state) and reset of the
device. During reset/output disable the PLL feedback
loop is open and the internal VCO is tied to its lowest
frequency. The MPC9774 requires reset after any loss of
PLL lock. Loss of PLL lock may occur when the external
feedback path is interrupted. The length of the reset
pulse should be greater than one reference clock cycle
(CCLKx). The device is reset by the internal power–on
reset (POR) circuitry during power–up.
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
V
V
CC
CC
Type
VCO ÷ 16
VCO ÷ 4
VCO ÷ 8
VCO ÷ 8
QA[4:0]
PLL reference clock
Alternative PLL reference clock
PLL feedback signal input, connect to QFB
LVCMOS clock reference select
VCO operating frequency select
PLL enable/PLL bypass mode select
Output enable/disable (high-impedance tristate) and device reset
Output enable/clock stop (logic low state)
Frequency divider select for bank A outputs
Frequency divider select for bank B outputs
Frequency divider select for bank C outputs
Frequency divider select for the QFB output
Clock outputs (Bank A)
Clock outputs (Bank B)
Clock outputs (Bank C)
PLL feedback output. Connect to FB_IN.
Negative power supply
PLL positive power supply (analog power supply). It is recommended to use an external RC filter
for the analog power supply pin V
Positive power supply for I/O and core. All V
supply for correct operation
VCO_SEL
0
0
1
1
0
FSEL_B
0
1
0
1
3
CC_PLL.
VCO ÷ 16
VCO ÷ 4
VCO ÷ 8
VCO ÷ 8
QB[4:0]
Please see applications section for details.
Function
CC
Selects CCKL1 as PLL reference signal input
Selects VCO ÷ 4. The VCO frequency is scaled by a
factor of 4 (low input frequency range).
Normal operation mode with PLL enabled.
Outputs enabled (active)
Outputs enabled (active)
pins must be connected to the positive power
VCO_SEL
0
0
1
1
FSEL_C
1
0
1
0
1
MPC9774
VCO ÷ 12
VCO ÷ 16
VCO ÷ 24
VCO ÷ 8
QC[3:0]
MOTOROLA