ISL12024IBZ-T Intersil, ISL12024IBZ-T Datasheet - Page 18

• Manufacturer Part Number: ISL12024IBZ-T
• Description: IC RTC/CALENDAR EEPROM 8-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/EEPROMr

Specifications of ISL12024IBZ-T

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL12024IBZ-TTR

Acknowledge Polling
Disabling of the inputs during non-volatile write cycles can
be used to take advantage of the 12ms (typ) write cycle time.
Once the stop condition is issued to indicate the end of the
master’s byte load operation, the ISL12024 initiates the
internal non-volatile write cycle. Acknowledge polling can
begin immediately. To do this, the master issues a start
condition followed by the Memory Array Slave Address Byte
for a write or read operation (AEh or AFh). If the ISL12024 is
still busy with the non-volatile write cycle, then no ACK will
be returned. When the ISL12024 has completed the write
operation, an ACK is returned and the host can proceed with
the read or write operation. See the flow chart in
Figure 20. Note: Do not use the CCR Slave byte (DEh or
DFh) for Acknowledge Polling.
Read Operations
There are three basic read operations: Current Address
Read, Random Read and Sequential Read.
Current Address Read
Internally the ISL12024 contains an address counter that
maintains the address of the last word read incremented by
one. Therefore, if the last read was to address n, the next
read operation would access data from address n+1. On
power-up, the 16-bit address is initialized to 00h. In this way,
a current address read immediately after the power-on reset
can download the entire contents of memory starting at the
first location. Upon receipt of the Slave Address Byte with
the R/W bit set to one, the ISL12024 issues an
acknowledge, then transmits 8 data bits. The master
terminates the read operation by not responding with an
acknowledge during the ninth clock and issuing a stop
condition. See Figure 19 for the address, acknowledge, and
data transfer sequence.
SIGNALS FROM
SIGNALS FROM
THE MASTER
THE SLAVE
SDA BUS
A
R
S
T
T
18
1
ADDRESS
SLAVE
1
1
1
0
A
C
K
FIGURE 18. PAGE WRITE SEQUENCE
0 0 0 0 0 0 0
ADDRESS 1
WORD
ISL12024
A
C
K
ADDRESS 0
WORD
SIGNALS FROM
SIGNALS FROM
THE MASTER
FIGURE 19. CURRENT ADDRESS READ SEQUENCE
THE SLAVE
FIGURE 20. ACKNOWLEDGE POLLING SEQUENCE
ISSUE MEMORY ARRAY SLAVE
CYCLE COMPLETE. CONTINUE
SDA BUS
AFH (READ) OR AEH (WRITE)
COMMAND SEQUENCE?
NON-VOLATILE WRITE
ENTER ACK POLLING
NORMAL READ OR
WRITE COMMAND
COMPLETED BY
A
C
K
ADDRESS BYTE
ISSUING STOP.
ISSUE START
BYTE LOAD
RETURNED?
SEQUENCE
CONTINUE
PROCEED
1 ≤ n ≤ 16 for EEPROM ARRAY
1 ≤ n ≤ 8 for CCR
ACK
DATA
(1)
S
T
A
R
T
YES
YES
1
ADDRESS
SLAVE
1
1
1
NO
NO
1
DATA
A
C
K
(n)
ISSUE STOP
ISSUE STOP
DATA
A
C
K
S
O
P
August 18, 2008
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FN6370.3
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