ISL12024IBZ-T Intersil, ISL12024IBZ-T Datasheet - Page 4

• Manufacturer Part Number: ISL12024IBZ-T
• Description: IC RTC/CALENDAR EEPROM 8-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/EEPROMr

Specifications of ISL12024IBZ-T

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL12024IBZ-TTR

AC Electrical Specifications
EEPROM Specifications
Serial Interface (I
DC Electrical Specifications
SYMBOL
EEPROM Endurance
EEPROM Retention
Hysteresis SDA and SCL Input Buffer Hysteresis
t
t
t
t
t
t
SYMBOL
HD:DAT
SU:STO
HD:STO
SU:STA
HD:STA
SU:DAT
t
t
t
f
HIGH
LOW
SCL
t
BUF
t
t
AA
DH
V
IN
V
I
V
I
LO
OL
LI
IH
IL
SCL Frequency
Pulse width Suppression Time at
SDA and SCL Inputs
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must be Free
Before the Start of a New
Transmission
Clock LOW Time
Clock HIGH Time
START Condition Set-up Time
START Condition Hold Time
Input Data Set-up Time
Input Data Hold Time
STOP Condition Set-up Time
STOP Condition Hold Time for
Read, or Volatile Only Write
Output Data Hold Time
SDA, and SCL Input Buffer LOW
Voltage
SDA, and SCL Input Buffer HIGH
Voltage
SDA Output Buffer LOW Voltage
Input Leakage Current on SCL
I/O Leakage Current on SDA
PARAMETER
PARAMETER
PARAMETER
2
C) Specifications
4
Temperature ≤ +75°C
Any pulse narrower than the max spec is
suppressed.
SCL falling edge crossing 30% of V
exits the 30% to 70% of V
SDA crossing 70% of V
condition, to SDA crossing 70% of V
the following START condition.
Measured at the 30% of V
Measured at the 70% of V
SCL rising edge to SDA falling edge. Both
crossing 70% of V
From SDA falling edge crossing 30% of V
SCL falling edge crossing 70% of V
From SDA exiting the 30% to 70% of V
window, to SCL rising edge crossing 30% of
V
From SCL rising edge crossing 70% of V
SDA entering the 30% to 70% of V
From SCL rising edge crossing 70% of V
SDA rising edge crossing 30% of V
From SDA rising edge to SCL falling edge. Both
crossing 70% of V
From SCL falling edge crossing 30% of V
until SDA enters the 30% to 70% of V
DD
.
I
V
V
OL
TEST CONDITIONS
IN
IN
= 4mA
= 5.5V
= 5.5V
TEST CONDITIONS
TEST CONDITIONS
DD
DD
ISL12024
.
.
DD
DD
DD
DD
during a STOP
window.
crossing.
crossing.
DD
DD
DD
DD
DD
DD
, until SDA
window.
.
.
DD
during
window.
DD
DD
DD
DD
2,000,000
(Note 12)
, to
,
to
to
MIN
50
0.05 x V
0.7 x V
(Note 12)
MIN
-0.3
(Note 12)
0
1300
1300
MIN
600
600
100
600
600
600
DD
0
0
DD
TYP
TYP
TYP
100
100
(Note 12) UNITS NOTES
MAX
400
900
50
0.3 x V
V
(Note 12)
MAX
DD
MAX
0.4
+ 0.3
DD
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
August 18, 2008
UNITS
Cycles
Years
UNITS
nA
nA
FN6370.3
V
V
V
V