ISL12024IBZ-T Intersil, ISL12024IBZ-T Datasheet - Page 19

• Manufacturer Part Number: ISL12024IBZ-T
• Description: IC RTC/CALENDAR EEPROM 8-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/EEPROMr

Specifications of ISL12024IBZ-T

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL12024IBZ-TTR

It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read operation,
the master must either issue a stop condition during the
ninth cycle or hold SDA HIGH during the ninth clock cycle
and then issue a stop condition.
Random Read
Random read operations allow the master to access any
location in the ISL12024. Prior to issuing the Slave Address
Byte with the R/W bit set to zero, the master must first
perform a “dummy” write operation.
The master issues the start condition and the slave address
byte, receives an acknowledge, then issues the word
address bytes. After acknowledging receipt of each word
address byte, the master immediately issues another start
condition and the slave address byte with the R/W bit set to
one. This is followed by an acknowledge from the device and
then by the 8-bit data word. The master terminates the read
operation by not responding with an acknowledge and then
issuing a stop condition. See Figure 21 for the address,
acknowledge and data transfer sequence.
In a similar operation called “Set Current Address,” the
device sets the address if a stop is issued instead of the
second start shown in Figure 21. The ISL12024 then goes
into Standby Power Mode after the stop and all bus activity
will be ignored until a start is detected. This operation loads
SIGNALS FROM
SIGNALS FROM
SIGNALS FROM
SIGNALS FROM
THE MASTER
THE MASTER
THE SLAVE
THE SLAVE
SDA BUS
SDA BUS
19
S
A
R
T
T
1
ADDRESS
SLAVE
ADDRESS
SLAVE
1
FIGURE 21. RANDOM ADDRESS READ SEQUENCE
1
A
C
K
FIGURE 22. SEQUENTIAL READ SEQUENCE
1
1
0
A
C
K
DATA
0 0 0 0 0 0 0
(1)
ADDRESS 1
WORD
ISL12024
A
C
K
A
C
K
ADDRESS 0
DATA
(2)
the new address into the address counter. The next Current
Address Read operation will read from the newly loaded
address. This operation could be useful if the master knows
the next address it needs to read, but is not ready for the
data.
Sequential Read
Sequential reads can be initiated as either a current address
read or random address read. The first data byte is
transmitted as with the other modes; however, the master
now responds with an acknowledge, indicating it requires
additional data. The device continues to output data for each
acknowledge received. The master terminates the read
operation by not responding with an acknowledge and then
issuing a stop condition.
The data output is sequential, with the data from address n
followed by the data from address n + 1. The address
counter for read operations increments through all page and
column addresses, allowing the entire memory contents to
be serially read during one operation. At the end of the
address space the counter “rolls over” to the start of the
address space and the ISL12024 continues to output data
for each acknowledge received. See Figure 22 for the
acknowledge and data transfer sequence.
WORD
A
C
K
A
C
K
(n is any integer greater than 1)
S
T
A
R
T
1
ADDRESS
DATA
SLAVE
(n-1)
1
1
1
1
A
C
K
A
C
K
DATA
DATA
(n)
S
O
P
T
O
S
T
P
August 18, 2008
FN6370.3