ISL1209IU10Z Intersil, ISL1209IU10Z Datasheet - Page 4

• Manufacturer Part Number: ISL1209IU10Z
• Description: IC RTC LP BATT BACK SRAM 10MSOP
• Manufacturer: Intersil
• Type: Clock/Calendar/NVSRAMr

Specifications of ISL1209IU10Z

• Memory Size: 2B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
NOTES:
2
V
V
Hysteresis
V
Cpin
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cb
Rpu
1. IRQ & F
2. LPMODE = 0 (default).
3. In order to ensure proper timekeeping, the V
4. Typical values are for T = +25°C and 3.3V supply voltage.
5. V
SCL
IN
AA
BUF
LOW
HIGH
SU:STA
HD:STA
SU:DAT
HD:DAT
SU:STO
HD:STO
DH
R
F
SYMBOL
C Interface Specifications
IL
IH
OL
SUP
= V
OUT
DD
SDA and SCL input buffer LOW
voltage
SDA and SCL input buffer HIGH
voltage
SDA and SCL input buffer hysteresis
SDA output buffer LOW voltage,
sinking 3mA
SDA and SCL pin capacitance
SCL frequency
Pulse width suppression time at SDA
and SCL inputs
SCL falling edge to SDA output data
valid
Time the bus must be free before the
start of a new transmission
Clock LOW time
Clock HIGH time
START condition setup time
START condition hold time
Input data setup time
Input data hold time
STOP condition setup time
STOP condition hold time
Output data hold time
SDA and SCL rise time
SDA and SCL fall time
Capacitive loading of SDA or SCL
SDA and SCL bus pull-up resistor
off-chip
and EVDET Inactive.
if in V
DD
PARAMETER
Mode, V
4
SUP
=V
Test Conditions:V
BAT
if in V
DD SR-
BAT
V
T
V
Any pulse narrower than the max spec is
suppressed.
SCL falling edge crossing 30% of V
exits the 30% to 70% of V
SDA crossing 70% of V
condition, to SDA crossing 70% of V
the following START condition.
Measured at the 30% of V
Measured at the 70% of V
SCL rising edge to SDA falling edge. Both
crossing 70% of V
From SDA falling edge crossing 30% of V
SCL falling edge crossing 70% of V
From SDA exiting the 30% to 70% of V
window, to SCL rising edge crossing 30% of
V
From SCL falling edge crossing 30% of V
SDA entering the 30% to 70% of V
From SCL rising edge crossing 70% of V
SDA rising edge crossing 30% of V
From SDA rising edge to SCL falling edge. Both
crossing 70% of V
From SCL falling edge crossing 30% of V
until SDA enters the 30% to 70% of V
From 30% to 70% of V
From 70% to 30% of V
Total on-chip and off-chip
Maximum is determined by t
For Cb = 400pF, max is about 2~2.5kΩ.
For Cb = 40pF, max is about 15~20kΩ
A
DD
OUT
DD.
specification must be followed.
= +25°C, f = 1MHz, V
Mode.
DD
= 5V, I
= 0V
= +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified.
OL
ISL1209
TEST CONDITIONS
= 3mA
DD
DD
.
.
DD.
DD.
DD
DD
DD
DD
DD
during a STOP
= 5V, V
R
window.
crossing.
crossing.
and t
DD
DD
DD
F
IN
DD
DD
.
DD
, until SDA
= 0V,
window.
.
.
DD
during
window.
DD
DD
DD
DD
, to
,
to
to
0.1 x Cb
0.1 x Cb
0.05 x
0.7 x
1300
1300
V
V
20 +
20 +
MIN
-0.3
600
600
600
100
600
600
20
10
DD
DD
0
1
(Note 4)
TYP
V
MAX
0.3 x
V
400
900
900
300
300
400
DD
0.3
0.4
10
50
DD
+
October 17, 2006
UNITS
FN6109.4
kHz
pF
pF
kΩ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
V
V