DS1302Z+ Maxim Integrated Products, DS1302Z+ Datasheet - Page 8

• Manufacturer Part Number: DS1302Z+
• Description: IC TIMEKEEPER W/CHARGER 8-SOIC
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/Trickle-Chargerr

Specifications of DS1302Z+

• Memory Size: 31B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: 3-Wire Serial
• Voltage - Supply: 2 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Function: Clock/Calendar/Trickle Charger/NV Timekeeping RAM
• Rtc Memory Size: 31 Byte
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: Serial (3-Wire)
• Supply Current: 1.2 mA
• Clock Format: HH
• Clock Ic Type: RTC
• Ic Interface Type: 3 Wire
• Memory Configuration: 31 X 8
• Supply Voltage Range: 2V To 5.5V
• Digital Ic Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CLOCK/CALENDAR BURST MODE
The clock/calendar command byte specifies burst mode operation. In this mode, the first eight clock/calendar
registers can be consecutively read or written (see Table 3) starting with bit 0 of address 0.
If the write-protect bit is set high when a write clock/calendar burst mode is specified, no data transfer will occur to
any of the eight clock/calendar registers (this includes the control register). The trickle charger is not accessible in
burst mode.
At the beginning of a clock burst read, the current time is transferred to a second set of registers. The time
information is read from these secondary registers, while the clock may continue to run. This eliminates the need to
re-read the registers in case of an update of the main registers during a read.
RAM
The static RAM is 31 x 8 bytes addressed consecutively in the RAM address space.
RAM BURST MODE
The RAM command byte specifies burst mode operation. In this mode, the 31 RAM registers can be consecutively
read or written (see Table 3) starting with bit 0 of address 0.
REGISTER SUMMARY
A register data format summary is shown in Table 3.
CRYSTAL SELECTION
A 32.768kHz crystal can be directly connected to the DS1302 via pins 2 and 3 (X1, X2). The crystal selected for
use should have a specified load capacitance (C
layout consideration, refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks.
Figure 4. Data Transfer Summary
SCLK
CE
I/O
SCLK
CE
I/O
R/
W
R/
W
NOTE: IN BURST MODE, CE IS KEPT HIGH AND ADDITIONAL SCLK CYCLES ARE SENT UNTIL THE END OF THE BURST.
A0
A0
A1
A1
A2
A2
A3
A3
A4
SINGLE-BYTE WRITE
SINGLE-BYTE READ
A4
R/
R/
C
C
L
) of 6pF. For more information on crystal selection and crystal
1
1
8 of 13
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7