ISL12058IUZ Intersil, ISL12058IUZ Datasheet - Page 12

• Manufacturer Part Number: ISL12058IUZ
• Description: IC RTC/CALENDAR I2C-BUS 8-MSOP
• Manufacturer: Intersil
• Type: Clock/Calendar/Alarmr

Specifications of ISL12058IUZ

• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -

B. Also the ALME bit must be set as follows:
xx indicate other control bits and these bit can be set to 0 or
1.
After these registers are set, the Alarm1 interrupt will be
generated when the RTC advances to exactly 11:30am on
January 1 (after seconds changes from 59 to 00) by setting
the A1F bit in the status register to “1” and also bringing the
IRQ/F
Alarm2 Registers
Addresses [Address 12h to 14h]
The Alarm2 register bytes are set up identical to the RTC
register bytes except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (minutes, hour, and date/day) are used to
make the comparison. Note that there are no alarm bytes for
second, month and year. When all the enable bits are set to
“0” with ALM2E set to “1”, the Alarm2 will triggered once a
minute when second hits “00”.
The Alarm2 function works as a comparison between the
Alarm2 registers and the RTC registers. As the RTC
advances, the Alarm2 will be triggered once a match occurs
between the Alarm2 registers and the RTC registers. Any
one Alarm2 register, multiple registers, or all registers can be
enabled for a match.
To clear an Alarm2, the A2F status bit can be set to “0” with a
write or use the ARST bit auto reset function.
REGISTER
REGISTER
CONTROL
ALARM1
A1MO
A1DW
A1MN
A1HR
A1SC
A1DT
INT
OUT
output low.
7 6 5 4 3 2 1 0 HEX
0 0 0 0 0 0 0 0
1 0 1 1 0 0 0 0
1 0 0 1 0 0 0 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0 HEX
0 1 x
x
BIT
x 1 0 1
BIT
12
B0h Minutes set to 30,
00h Seconds disabled
91h Hours set to 11,
81h Date set to 1,
81h Month set to 1,
00h Day of week
45h Enable Alarm1,
enabled
enabled
enabled
enabled
disabled
and Alarm1
Interrupt to
IRQ/F
DESCRIPTION
DESCRIPTION
OUT
ISL12058
Following is example of Alarm2 Interrupt.
Example – A single alarm will occur on every Monday at
20:00 military time (Monday is when DW = 1).
A. Set Alarm registers as follows:
After these registers are set, an alarm will be generated when
the RTC advances to exactly 20:00 on Monday (after minutes
changes from 59 to 00) by setting the A2F bit in the status
register to “1”.
I
The ISL12058 supports a bi-directional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is the master
and the device being controlled is the slave. The master
always initiates data transfers and provides the clock for
both transmit and receive operations. Therefore, the
ISL12058 operates as a slave device in all applications.
All communication over the I
sending the MSB of each byte of data first.
A2DW/DT A2M2
REGISTER
2
A2DW/DT
ALARM2
C Serial Interface
TABLE 7. ALARM2 INTERRUPT WITH ENABLE BITS
A2MN
A2HR
0
0
0
0
1
0
0
0
0
1
1
1
1
SELECTION
7 6 5 4 3 2 1 0 HEX
0 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0
1 1 0 0 0 0 0 1
0
1
0
0
0
1
1
0
1
1
1
0
1
A2M3
0
0
1
0
0
1
0
1
1
1
0
1
1
BIT
A2M4
2
0
0
0
1
1
0
1
1
1
0
1
1
1
C interface is conducted by
Match Minute, Hour, and Date
Match Minute, Hour, and Day
Every Minute (Second=00)
Match Minute and Hour
Match Minute and Hour
Match Minute and Date
Match Minute and Day
Match Hour and Date
Match Hour and Day
C1h Day set to Monday,
00h Minutes disabled
E0h Hours set to 20,
ALARM2 Interrupt
Match Minute
Match Hour
Match Date
Match Day
enabled
enabled
DESCRIPTION
June 15, 2009
FN6756.0