MAX19713ETN+ Maxim Integrated Products, MAX19713ETN+ Datasheet - Page 6

• Manufacturer Part Number: MAX19713ETN+
• Description: IC ANLG FRONT END 45MSPS 56-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX19713ETN+

• Number Of Bits: 10
• Number Of Channels: 2
• Power (watts): 91.8mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3V
• Package / Case: 56-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ELECTRICAL CHARACTERISTICS (continued)
(V
= -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, C
C
10-Bit, 45Msps, Full-Duplex
Analog Front-End
6
Integral Nonlinearity
Supply Current
AUXILIARY DACs (DAC1, DAC2, DAC3)
Resolution
Integral Nonlinearity
Differential Nonlinearity
Output-Voltage Low
Output-Voltage High
DC Output Impedance
Settling Time
Glitch Impulse
Rx ADC–Tx DAC TIMING CHARACTERISTICS
CLK Rise to Channel-I Output Data
Valid
CLK Fall to Channel-Q Output
Data Valid
I- D AC D ATA to C LK Fal l S etup Ti m e
Q-DAC DATA to CLK Rise Setup
Time
CLK Fall to I-DAC Data Hold Time
CLK Rise to Q-DAC Data Hold
Time
CLK Duty Cycle
CLK Duty-Cycle Variation
Digital Output Rise/Fall Time
SERIAL-INTERFACE TIMING CHARACTERISTICS (Figures 6 and 8, Note 6)
Falling Edge of CS /WAKE to Rising
Edge of First SCLK Time
DIN to SCLK Setup Time
DIN to SCLK Hold Time
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Period
SCLK to CS /WAKE Setup Time
CS /WAKE High Pulse Width
CS /WAKE High to DOUT Active
High
COM
DD
_______________________________________________________________________________________
= 3V, OV
= 0.33µF, C
PARAMETER
DD
= 1.8V, internal reference (1.024V), C
L
< 5pF on all aux-DAC outputs, T
SYMBOL
t
t
t
t
DNL
t
t
V
V
t
DOQ
t
INL
INL
t
DSQ
DHQ
CSW
CSS
t
t
t
t
t
CSD
t
DOI
DHI
D S I
DS
DH
CH
CP
CS
N
CL
OH
OL
A
= T
L
From code 100 to code 4000
Guaranteed monotonic over code 100 to
code 4000 (Note 6)
R
R
DC output at midscale
From code 1024 to code 3072, within ±10
LSB
From code 0 to code 4095
Figure 3 (Note 6)
Figure 3 (Note 6)
Fi g ur e 5 ( N ote 6)
Figure 5 (Note 6)
Figure 5 (Note 6)
Figure 5 (Note 6)
20% to 80%
Bit AD0 set
≈ 10pF on all digital outputs, f
L
L
MIN
> 200k Ω
> 200k Ω
to T
MAX
, unless otherwise noted. Typical values are at T
CONDITIONS
CLK
= 45MHz (50% duty cycle), Rx ADC input amplitude
MIN
2.57
-1.0
5.5
6.5
12
10
10
10
10
25
25
50
10
80
0
0
0
±1.25
±0.65
±0.6
TYP
±10
210
200
8.2
9.5
2.4
24
50
4
1
A
= +25°C.) (Note 1)
MAX
+1.2
12.5
13.6
0.2
REFP
= C
UNITS
nV
REFN
LSB
LSB
LSB
Bits
µA
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
Ω
V
V
•
s
=