AD7980BRMZ Analog Devices Inc, AD7980BRMZ Datasheet - Page 16

• Manufacturer Part Number: AD7980BRMZ
• Description: ADC 16BIT 1MSPS 1.25LSB 10-MSOP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7980BRMZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 16
• Sampling Rate (per Second): 1M
• Number Of Converters: 1
• Power Dissipation (max): 10mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP (0.118", 3.00mm Width)
• Resolution (bits): 16bit
• Sampling Rate: 1MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 2.375V To 2.625V
• Supply Current: 350pA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7980
VOLTAGE REFERENCE INPUT
The AD7980 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source, for example,
a reference buffer using the
chip capacitor is appropriate for optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift
If desired, a reference-decoupling capacitor value as small as
2.2 μF can be used with a minimal impact on performance,
especially DNL.
Regardless, there is no need for an additional lower value ceramic
decoupling capacitor (for example, 100 nF) between the REF
and GND pins.
POWER SUPPLY
The AD7980 uses two power supply pins: a core supply, VDD, and
a digital input/output interface supply, VIO. VIO allows direct
interface with any logic between 1.8 V and 5.0 V. To reduce the
number of supplies needed, VIO and VDD can be tied together.
The AD7980 is independent of power supply sequencing between
VIO and VDD. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in Figure 29.
To ensure optimum performance, VDD should be roughly half
of REF, the voltage reference input. For example, if REF is 5.0 V,
VDD should be set to 2.5 V (±5%).
The AD7980 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate. This makes the part ideal for low sampling
rate (even of a few Hz) and low battery-powered applications.
80
75
70
65
60
55
1
Figure 29. PSRR vs. Frequency
10
FREQUENCY (kHz)
AD8031
or the AD8605, a ceramic
100
ADR43x
reference.
1000
Rev. B | Page 16 of 28
DIGITAL INTERFACE
Though the AD7980 has a reduced number of pins, it offers
flexibility in its serial interface modes.
The AD7980, when in CS mode, is compatible with SPI, QSPI,
and digital hosts. This interface can use either a 3-wire or 4-wire
interface. A 3-wire interface using the CNV, SCK, and SDO
signals minimizes wiring connections useful, for instance, in
isolated applications. A 4-wire interface using the SDI, CNV,
SCK, and SDO signals allows CNV, which initiates the
conversions, to be independent of the readback timing (SDI).
This is useful in low jitter sampling or simultaneous sampling
applications.
The AD7980, when in chain mode, provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The CS mode is selected if
SDI is high, and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is selected.
In either mode, the AD7980 offers the flexibility to optionally
force a start bit in front of the data bits. This start bit can be
used as a busy signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a busy indicator,
the user must time out the maximum conversion time prior to
readback.
The busy indicator feature is enabled
 In the CS mode if CNV or SDI is low when the ADC
 In the chain mode if SCK is high during the CNV rising edge
conversion ends (see Figure 34 and Figure 38).
(see Figure 42).
10.000
1.000
0.100
0.010
0.001
10000
Figure 30. Operating Currents vs. Sampling Rate
SAMPLING RATE (SPS)
100000
I
I
I
VDD
REF
VIO
1000000