AD7980BRMZ Analog Devices Inc, AD7980BRMZ Datasheet - Page 22

• Manufacturer Part Number: AD7980BRMZ
• Description: ADC 16BIT 1MSPS 1.25LSB 10-MSOP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7980BRMZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 16
• Sampling Rate (per Second): 1M
• Number Of Converters: 1
• Power Dissipation (max): 10mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP (0.118", 3.00mm Width)
• Resolution (bits): 16bit
• Sampling Rate: 1MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 2.375V To 2.625V
• Supply Current: 350pA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7980
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7980s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications or
for systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register.
A connection diagram example using three AD7980s is shown
in Figure 41, and the corresponding timing is given in Figure 42.
CNV = SDI
AQUISITION
SCK
SDO
SDO
SDO
A
B
C
t
HSDICNV
= SDI
= SDI
A
B
C
CONVERSION
t
t
CONV
t
DSDOSDI
SSDICNV
t
t
EN
DSDOSDI
SDI
t
HSDO
1
t
SSDISCK
AD7980
CNV
SCK
D
D
D
A
C
B
2
A
15
15
15
D
D
D
C
SDO
B
3
A
14
14
14
Figure 42. Chain Mode with Busy Indicator Serial Interface Timing
t
Figure 41. Chain Mode with Busy Indicator Connection Diagram
DSDO
D
D
t
D
SCKH
C
4
t
A
B
HSDISC
13
13
13
SDI
15
AD7980
t
SCK
CNV
SCK
B
D
D
D
16
C
B
A
1
1
1
Rev. B | Page 22 of 28
t
SCKL
SDO
D
D
D
17
C
A
B
0
0
0
D
D
B
18
A
15
15
SDI
t
CYC
AQUISITION
D
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the SDO pin of the ADC closest to
the digital host (see the AD7980 ADC labeled C in Figure 41) is
driven high. This transition on SDO can be used as a busy
indicator to trigger the data readback controlled by the digital
host. The AD7980 then enters the acquisition phase and powers
down. The data bits stored in the internal shift register are
clocked out, MSB first, by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 × N + 1 clocks are required to
readback the N ADCs. Although the rising edge can be used to
capture the data, a digital host using the SCK falling edge allows a
faster reading rate and, consequently, more AD7980s in the chain,
provided the digital host has an acceptable hold time.
D
19
B
A
14
AD7980
14
t
ACQ
CNV
SCK
C
31
SDO
D
D
32
B
A
1
1
D
D
33
B
A
0
0
D
34
A
CONVERT
DATA IN
IRQ
CLK
15
DIGITAL HOST
D
35
A
14
47
D
t
DSDOSDI
48
A
1
t
DSDOSDI
t
DSDODSI
D
49
A
0