AD7980BRMZ Analog Devices Inc, AD7980BRMZ Datasheet - Page 21

• Manufacturer Part Number: AD7980BRMZ
• Description: ADC 16BIT 1MSPS 1.25LSB 10-MSOP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7980BRMZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 16
• Sampling Rate (per Second): 1M
• Number Of Converters: 1
• Power Dissipation (max): 10mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP (0.118", 3.00mm Width)
• Resolution (bits): 16bit
• Sampling Rate: 1MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 2.375V To 2.625V
• Supply Current: 350pA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CHAIN MODE, WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7980s on a
3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multi-converter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7980s is shown in
Figure 39, and the corresponding timing is given in Figure 40.
SDO
AQUISITION
SDI
A
= SDI
SDO
A
CNV
SCK
t
HSDICNV
= 0
B
B
CONVERSION
t
SSDICNV
t
CONV
t
EN
SDI
AD7980
t
HSDO
CNV
SCK
Figure 40. Chain Mode Without Busy Indicator Serial Interface Timing
Figure 39. Chain Mode Without Busy Indicator Connection Diagram
A
D
D
A
B
15
15
1
t
SDO
SSDISCK
D
D
2
A
B
14
14
t
DSDO
D
D
3
A
B
13
13
Rev. B | Page 21 of 28
t
SCKL
t
SDI
HSDISC
14
AD7980
CNV
SCK
B
D
D
t
15
CYC
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the Busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7980 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are clocked by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 × N clocks are required to
readback the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and, consequently, more AD7980s in the chain, provided
the digital host has an acceptable hold time. The maximum
conversion rate may be reduced due to the total readback time.
A
B
1
1
AQUISITION
t
SCK
SDO
t
t
SCKH
D
D
16
ACQ
A
B
0
0
D
17
A
15
CONVERT
DATA IN
CLK
D
18
A
DIGITAL HOST
14
30
D
31
A
1
D
32
A
0
AD7980