ADC08D500CIYB/NOPB National Semiconductor, ADC08D500CIYB/NOPB Datasheet - Page 2

• Manufacturer Part Number: ADC08D500CIYB/NOPB
• Description: IC ADC 8BIT 500MSPS DUAL 128LQFP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D500CIYB/NOPB

• Number Of Bits: 8
• Sampling Rate (per Second): 500M
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 1.78W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC08D500CIYB; *ADC08D500CIYB/NOPB; ADC08D500CIYB

© 2011 National Semiconductor Corporation
High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D
Converter
General Description
The ADC08D500 is a dual, low power, high performance
CMOS analog-to-digital converter that digitizes signals to 8
bits resolution at sampling rates up to 500 MSPS. Consuming
a typical 1.4 Watts at 500 MSPS from a single 1.9 Volt supply,
this device is guaranteed to have no missing codes over the
full operating temperature range. The unique folding and in-
terpolating architecture, the fully differential comparator de-
sign, the innovative design of the internal sample-and-hold
amplifier and the self-calibration scheme enable a very flat
response of all dynamic parameters beyond Nyquist, produc-
ing a high 7.5 ENOB with a 250 MHz input signal and a 500
MHz sample rate while providing a 10
matting is offset binary and the LVDS digital outputs are
compatible with IEEE 1596.3-1996, with the exception of an
adjustable common mode voltage between 0.8V and 1.2V.
Each converter has a 1:2 demultiplexer that feeds two LVDS
buses and reduces the output data rate on each bus to half
the sampling rate. The two converters can be interleaved and
used as a single 1 GSPS ADC.
The converter typically consumes less than 3.5 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced exposed pad LQFP and operates over the Indus-
trial (-40°C
≤
T
A
≤
+85°C) temperature range.
-18
201214
B.E.R. Output for-
ADC08D500
Features
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Key Specifications
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Applications
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Internal Sample-and-Hold
Single +1.9V ±0.1V Operation
Choice of SDR or DDR output clocking
Interleave Mode for 2x Sampling Rate
Multiple ADC Synchronization Capability
Guaranteed No Missing Codes
Serial Interface for Extended Control
Fine Adjustment of Input Full-Scale Range and Offset
Duty Cycle Corrected Sample Clock
Resolution
Max Conversion Rate
Bit Error Rate
ENOB @ 250 MHz Input
DNL
Power Consumption
— Operating
— Power Down Mode
Direct RF Down Conversion
Digital Oscilloscopes
Satellite Set-top boxes
Communications Systems
Test Instrumentation
500 MSPS (min)
March 25, 2011
±0.15 LSB (typ)
www.national.com
3.5 mW (typ)
7.5 Bits (typ)
1.4 W (typ)
10
-18
8 Bits
(typ)