ADC083000CIYB/NOPB National Semiconductor, ADC083000CIYB/NOPB Datasheet - Page 34

• Manufacturer Part Number: ADC083000CIYB/NOPB
• Description: IC ADC 8BIT 3GSPS LP 128-LQFP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC083000CIYB/NOPB

• Number Of Bits: 8
• Sampling Rate (per Second): 3G
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 2.3W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC083000CIYB; *ADC083000CIYB/NOPB; ADC083000CIYB

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2.4.2 Calibration
The ADC083000 calibration must be run to achieve specified
performance. The calibration procedure is run upon power-up
and can be run any time on command. The calibration pro-
cedure is exactly the same whether there is an input clock
present upon power up or if the clock begins some time after
application of power. The CalRun output indicator is high
while a calibration is in progress. Note that the DCLK outputs
are not active during a calibration cycle, therefore it is not
recommended as a system clock.
2.4.2.1 Power-On Calibration
Power-on calibration begins after a time delay following the
application of power. This time delay is determined by the
setting of CalDly, as described in the Calibration Delay Sec-
tion, below.
The calibration process will be not be performed if the CAL
pin is high at power up. In this case, the calibration cycle will
not begin until the on-command calibration conditions are
met. The ADC083000 will function with the CAL pin held high
at power up, but no calibration will be done and performance
will be impaired. A manual calibration, however, may be per-
formed after powering up with the CAL pin high. See On-
Command Calibration Section 2.4.2.2.
The internal power-on calibration circuitry comes up in an un-
known logic state. If the input clock is not running at power up
and the power on calibration circuitry is active, it will hold the
analog circuitry in power down and the power consumption
will typically be less than 25 mW. The power consumption will
be normal after the clock starts.
2.4.2.2 On-Command Calibration
To initiate an on-command calibration, bring the CAL pin high
for a minimum of 80 input clock cycles after it has been low
for a minimum of 80 input clock cycles. Holding the CAL pin
high upon power up will prevent execution of power-on cali-
bration until the CAL pin is low for a minimum of 80 input clock
cycles, then brought high for a minimum of another 80 input
clock cycles. The calibration cycle will begin 80 input clock
cycles after the CAL pin is thus brought high. The CalRun
signal should be monitored to determine when the calibration
cycle has completed.
The minimum 80 input clock cycle sequences are required to
ensure that random noise does not cause a calibration to be-
gin when it is not desired. As mentioned in section 1.1 for best
performance, a calibration should be performed 20 seconds
or more after power up and repeated when the operating
temperature changes significantly relative to the specific sys-
tem design performance requirements. ENOB changes
slightly with increasing junction temperature and can be easily
corrected by performing an on-command calibration.
Considerations for a continuous DCLK and proper
CalRun operation:
•
During a Power-On calibration cycle, both the ADC and
the input termination resistor are calibrated. Because
dynamic performance changes slightly with junction
temperature, an On-Command calibration can be
executed to bring the performance of the ADC in line. By
default, On-Command calibration includes calibrating the
input termination resistance and the ADC. However, since
the input termination resistance changes only marginally
with temperature, the user has the option to disable the
input termination resistor trim (address: 1h, bit: 13, set to
1b), which will guarantee that the DCLK is continuously
present at the output during calibration. The Resistor Trim
Disable can be programmed in the Configuration Register
34
•
2.4.2.3 Calibration Delay
The CalDly input (pin 127) is used to select one of two delay
times after the application of power to the start of calibration,
as described in Section 1.1.1. The calibration delay values
allow the power supply to come up and stabilize before cali-
bration takes place. With no delay or insufficient delay, cali-
bration would begin before the power supply is stabilized at
its operating value and result in non-optimal calibration coef-
ficients. If the PD pin is high upon power-up, the calibration
delay counter will be disabled until the PD pin is brought low.
Therefore, holding the PD pin high during power up will further
delay the start of the power-up calibration cycle. The best
setting of the CalDly pin depends upon the power-on settling
time of the power supply.
Note that the calibration delay selection is not possible in the
Extended Control mode and the short delay time is used.
2.4.3 Output Edge Synchronization
DCLK signals are available to help latch the converter output
data into external circuitry. The output data can be synchro-
nized with either edge of these DCLK signals. That is, the
output data transition can be set to occur with either the rising
edge or the falling edge of the DCLK signal, so that either
edge of that DCLK signal can be used to latch the output data
into the receiving circuit.
When OutEdge (pin 4) is high, the output data is synchronized
with (changes with) the rising edge of the DCLK+ (pin 82).
When OutEdge is low, the output data is synchronized with
the falling edge of DCLK+.
At the very high speeds of which the ADC083000 is capable,
slight differences in the lengths of the DCLK and data lines
can mean the difference between successful and erroneous
data capture. The OutEdge pin is used to capture data on the
DCLK edge that best suits the application circuit and layout.
2.4.4 LVDS Output Level Control
The output level can be set to one of two levels with OutV
(pin3). The strength of the output drivers is greater with OutV
high. With OutV low there is less power consumption in the
output drivers, but the lower output level means decreased
noise immunity.
For short LVDS lines and low noise systems, satisfactory per-
formance may be realized with the OutV input low. If the LVDS
lines are long and/or the system in which the ADC083000 is
used is noisy, it may be necessary to tie the OutV pin high.
2.4.5 Power Down Feature
The Power Down pin (PD) allows the ADC083000 to be en-
tirely powered down. See Section 1.1.7 for details on the
power down feature.
The digital data (+/-) output pins are put into a high impedance
state when the PD pin for the respective channel is high. Upon
(address: 1h, bit 13) when in the Extended Control mode.
Refer to section 1.4 for register programming information.
When an on-command calibration is requested while using
the Aperture Adjust Circuitry through the Extended Control
Mode registers, we recommend that the Resistor Trim
Disable bit be set (address: 1h, bit: 13, set to 1b). This
allows continuous operation of all clocks in the ADC
including DCLK and proper operation of the CalRun
output. The Aperture Adjust Circuitry control is resident in
the Extended Control Mode registers (addresses: Dh and
Eh). Refer to section 1.4 for register programming
information.